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Registers
328
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.2.3
CIG_reg2 Register (offset = 8h) [reset = 0h]
CIG_reg2 is shown in
and described in
.
CIG HDMI Transparency Config Reg
Figure 1-221. CIG_reg2 Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
R-0h
15
14
13
12
11
10
9
8
Reserved
BL_LEVEL
R-0h
R/W-0h
7
6
5
4
3
2
1
0
BL_LEVEL
BL_ENABLE
TR_MODE_MASK
TR_ENABLE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-128. CIG_reg2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-12
Reserved
R
0h
Reserved
11-4
BL_LEVEL
R/W
0h
Blending Value Assigned to the video pixel's alpha if blending is
enabled.
3
BL_ENABLE
R/W
0h
Blending Enable
0: Disable Blending
1: Apply Blending
2-1
TR_MODE_MASK
R/W
0h
Transparency Color Mask Bit (Number of LSB bits to mask when
checking for pixel transparency)
0: No masking
1: Mask 1 LSB bit
2: Mask 2 LSB bits
3: Mask 3 LSB bits
0
TR_ENABLE
R/W
0h
Transparency Enable
0: Disable Transparency
1: Enable Transparency