Registers
471
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-225. VPDMA_int0_channel0_int_stat Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
INT_STAT_HQ_VID1_CH
ROMA
W
0h
The last read DMA transaction has occurred for channel
hq_vid1_chroma and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client
dei_1_chroma will now accept a new descriptor from the List
Manager. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
0
INT_STAT_HQ_VID1_LU
MA
W
0h
The last read DMA transaction has occurred for channel
hq_vid1_luma and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client
dei_1_luma will now accept a new descriptor from the List Manager.
This event will cause a one to be set in this register until cleared by
software. Write a 1 to this field to clear the value.
