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Registers
765
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.9.11 HD_VENC_D_cfg10 Register (offset = 28h) [reset = 0h]
HD_VENC_D_cfg10 is shown in
and described in
Frame Size Register
Figure 1-447. HD_VENC_D_cfg10 Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
LINES
R/W-0h
15
14
13
12
11
10
9
8
LINES
PIXELS
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
PIXELS
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-360. HD_VENC_D_cfg10 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
Reserved
R
0h
Reserved
23-12
LINES
R/W
0h
Defines the total number of lines per frame.
11-0
PIXELS
R/W
0h
Defines the total number of pixels per line.