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Description of the Subsystem
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SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.1.9 Reset
HDVPSS provides separate resets for each of the paths/modules.
The following sequence is used to reset the entire HDVPSS module:
1. Take VPDMA to standby via force standby MMR write. This disconnects master ports.
2. Ensure all VENCs are disabled via MMR writes.
3. Power down VENCs via appropriate MMR writes.
4. Shut down VENC clocks via MMR writes.
5. Shut down VIP clocks.
6. Shut down all module clocks by writing to all enable bits.
7. Reset all modules and Vencs by writing reset bits.
8. Request IDLE, on IDLE acknowledgement, clocks can be shut down.