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Registers
945
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.14.46 VIP_PARSER_port_b_vdet_vec Register (offset = B4h) [reset = 0h]
VIP_PARSER_port_b_vdet_vec is shown in
and described in
Each bit represents the VDET bit setting for Line Mux Mode
Figure 1-608. VIP_PARSER_port_b_vdet_vec Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PRTB_VDET_VEC
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-526. VIP_PARSER_port_b_vdet_vec Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
PRTB_VDET_VEC
R
0h
For Embedded Sync Only In Line Mux Mode.. each bit represents
the vdet value on Port B for the corresponding source id. This vector
is meaningless for 1x/2x/4x mux modes.