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Registers
487
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-230. VPDMA_int0_channel2_int_mask Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
INT_MASK_VIP1_MULT_
PORTB_SRC12
R/W
0h
The interrupt for Video Input 1 Port B Channel 12 should generate
an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event
to trigger the interrupt signal.
1
INT_MASK_VIP1_MULT_
PORTB_SRC11
R/W
0h
The interrupt for Video Input 1 Port B Channel 11 should generate
an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event
to trigger the interrupt signal.
0
INT_MASK_VIP1_MULT_
PORTB_SRC10
R/W
0h
The interrupt for Video Input 1 Port B Channel 10 should generate
an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event
to trigger the interrupt signal.