Registers
780
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.9.26 HD_VENC_D_cfg25 Register (offset = 64h) [reset = 0h]
HD_VENC_D_cfg25 is shown in
and described in
Compositor IF Control Register
Figure 1-462. HD_VENC_D_cfg25 Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
OSD_FID_ST1
R/W-0h
15
14
13
12
11
10
9
8
OSD_FID_ST1
Reserved
R/W-0h
R-0h
7
6
5
4
3
2
1
0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-375. HD_VENC_D_cfg25 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
Reserved
R
0h
Reserved
23-12
OSD_FID_ST1
R/W
0h
This parameter defines the frame line (for progressive mode) or top
field line (for interlaced mode) number at which the DTV_FID will
switch.
Progressive mode:
OSD_FID_ST1 = int ( (cfg010.lines – cfg023.osd_avd_vw1)/3 )
Interlace mode:
OSD_FID_ST1 = int ( (cfg010.lines/2 – cfg023.osd_avd_vw1)/3 )
11-0
Reserved
R
0h
Reserved
Note:
DTV_FID switches to both progressive and interlaced mode to indicate to internal processing
modules that a new frame/field is starting. The above OSD_FID_ST1 parameter setup configures the
DTV_FID to switch about 1/3 into the VBI period, giving sufficient timing margin for DMA set-up and video
pipeline fill-up prior to the next active video period.
