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A0
A1
A2
A3
B0
B1
B2
B3
A0
B0
A1
B1
A2
B2
A3
B3
Stream A
Stream B
2-Way Muxed
Stream
time
Internal Modules
161
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.2.8.2.7 Source Multiplexing
1.2.8.2.7.1 Multiplexing Scenarios
Some applications require multiple camera sources to be used at the same time. For example, video
surveillance systems can record and display multiple camera sources. For this type of device, one solution
would be to support N 8b or 16b data interfaces for each of N cameras. However, this solution does not
efficiently minimize pin count. One set of 8b or 16b interfaces has the bandwidth to support more than one
video source, depending on the resolution of the video.
is explanatory only and shows the
number of sources that can be multiplexed in one VIP for 8b and 16b interface modes. Note that it does
not reflect the capabilities of the VIP Parser design. In addition, the interface pixel clock rates are shown.
The VPDMA limits 16 camera sources to be saved to DDR per Pixel Clock Input Domain.
(1)
Blanking pixels are not used in the CIF clock rate calculations. Addition of blanking pixels would require a slightly higher clock
rate.
Table 1-57. Multiplexing Configurations and Pixel Clock Rates
Max Channels In Single 16b
Data Interface Mode
Max Channels In Dual 8b Data
Interface Mode - Interleaved
Channels per Single 8b Port.
One 16b VIP can be configured
to support two such 8b ports.
Interface Clock Rate (MHz)
HD Interlaced
2
1
148.5
D1 Interlaced
8
4
108.1
CIF Interlaced
n/a
n/a
n/a
HD Progressive
1
n/a
148.5
D1 Progressive
4
2
108.1
CIF Progressive
(1)
32
16
162.2
NOTE:
These Channel Density values reflect 1 VIP subsystem.
1.2.8.2.7.2 2-Way Multiplexing
For 2-Way Multiplexing, two embedded sync streams are interleaved a pixel at a time as shown in
.
Figure 1-111. 2-Way Multiplexing
The sync codeword, FF-00-00-XY, is replicated in both source streams. In 2-Way Multiplexing, the sizes of
both camera sources must be the same. Likewise, the Vertical Ancillary Data size for both sources must
be identical. However, the two streams are not necessarily sending the same pixel site in adjacent clock
cycles.