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Registers
436
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.35 intc_eoi Register (offset = A0h) [reset = 0h]
intc_eoi is shown in
and described in
End of Interrupt Register
Figure 1-291. intc_eoi Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EOI_VECTOR
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-202. intc_eoi Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
EOI_VECTOR
R/W
0h
Number associated with the ipgenericirq for intr output. There are 4
interrupt outputs Write 0x0 : Write to intr0 IP Generic Write 0x1 :
Write to intr1 IP Generic Write 0x2 : Write to intr2 IP Generic Write
0x3 : Write to intr3 IP Generic Any other write value is ignored.