Texas Instruments DM38x DaVinci, User Manual

Page: 477 / 956

www.ti.com
Registers
477 SPRUHI7A – December 2012 – Revised June 2016
Submit Documentation Feedback
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-227. VPDMA_int0_channel1_int_stat Register Field Descriptions (continued)
Bit Field Type Reset Description
5 INT_STAT_GRPX3_CLUT W 0h
The last read DMA transaction has occurred for channel grpx3_clut
and the channel is free to be updated for the next transfer. This will
fire before the destination has received the data as it will have just
been stored in the internal buffer. The client grpx3_clut_clt will now
accept a new descriptor from the List Manager. This event will cause
a one to be set in this register until cleared by software. Write a 1 to
this field to clear the value.
4 INT_STAT_GRPX2_CLUT W 0h
The last read DMA transaction has occurred for channel grpx2_clut
and the channel is free to be updated for the next transfer. This will
fire before the destination has received the data as it will have just
been stored in the internal buffer. The client grpx2_clut_clt will now
accept a new descriptor from the List Manager. This event will cause
a one to be set in this register until cleared by software. Write a 1 to
this field to clear the value.
3 INT_STAT_GRPX1_CLUT W 0h
The last read DMA transaction has occurred for channel grpx1_clut
and the channel is free to be updated for the next transfer. This will
fire before the destination has received the data as it will have just
been stored in the internal buffer. The client grpx1_clut_clt will now
accept a new descriptor from the List Manager. This event will cause
a one to be set in this register until cleared by software. Write a 1 to
this field to clear the value.
2 INT_STAT_GRPX3_STE
NCIL W 0h
The last read DMA transaction has occurred for channel
grpx3_stencil and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client grpx3_st
will now accept a new descriptor from the List Manager. This event
will cause a one to be set in this register until cleared by software.
Write a 1 to this field to clear the value.
1 INT_STAT_GRPX2_STE
NCIL W 0h
The last read DMA transaction has occurred for channel
grpx2_stencil and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client grpx2_st
will now accept a new descriptor from the List Manager. This event
will cause a one to be set in this register until cleared by software.
Write a 1 to this field to clear the value.
0 INT_STAT_GRPX1_STE
NCIL W 0h
The last read DMA transaction has occurred for channel
grpx1_stencil and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client grpx1_st
will now accept a new descriptor from the List Manager. This event
will cause a one to be set in this register until cleared by software.
Write a 1 to this field to clear the value.