AMD AMD5K86 User Manual Download

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Summary of Contents for AMD5K86

Page 1: ... AMD5K 86 Processor Technical Reference Manual AMD ...

Page 2: ...Technical Reference Manual AMD ...

Page 3: ...s of this publication or the information contained herein and reserves the right to make changes at any time without notice AMD disclaims responsibility for any consequences resulting from the use of the information included herein AMD the Arrow Logo and combinations thereof are trademarks of Advanced Micro Devices Inc and are protected in many countries throughout the world Am386 and Am486 are re...

Page 4: ... Retire 2 12 2 3 Cache Organization and Management 2 13 2 3 1 Instruction Cache 2 14 2 3 2 Data Cache 2 15 2 3 3 Cache Tags 2 16 2 3 4 Cache Line Fills 2 17 2 3 5 Cache Coherency 2 18 2 3 6 Snooping 2 21 Inquire Cycles 2 21 Internal Snooping 2 22 2 3 7 Buffers 2 23 Line Fill Buffers 2 23 Prefetch Cache 2 24 Store Buffer 2 24 Replacement and Invalidation Writeback Buffer 2 25 Snoop Writeback Buffer...

Page 5: ...pecific Registers MSRs 3 25 3 2 1 Machine Check Address Register MCAR 3 25 3 2 2 Machine Check Type Register MCTR 3 26 3 2 3 Time Stamp Counter TSC 3 27 3 2 4 Array Access Register AAR 3 27 3 2 5 Hardware Configuration Register HWCR 3 28 3 3 New Instructions 3 28 3 3 1 CPUID 3 29 3 3 2 CMPXCHG8B 3 32 3 3 3 MOV to and from CR4 3 33 3 3 4 RDTSC 3 34 3 3 5 RDMSR and WRMSR 3 35 3 3 6 RSM 3 37 3 3 7 ll...

Page 6: ... 2 14 BUSCHK Bus Check 5 47 5 2 15 CACHE Cacheable Access 5 50 5 2 16 CLK Bus Clock 5 53 5 2 17 D C Data or Code 5 54 5 2 18 D63 DO Data Bus 5 56 5 2 19 DP7 DPO Data Parity 5 58 5 2 20 EADS External Address Strobe 5 59 5 2 21 EWBE External Write Buffer Empty 5 63 5 2 22 FERR Floating Point Error 5 65 5 2 23 FLOSH Cache Flush 5 67 5 2 24 FRCMC Functional Redundancy Check Master Checker 5 70 5 2 25 ...

Page 7: ...139 5 3 4 Bus Speed and Typical DRAM Timing 5 140 5 3 5 Bus Cy le Priorities 5 140 5 4 Bus Cycle Timing 5 141 5 4 1 Timing Diagrams 5 141 5 4 2 Single Transfer Reads and Writes 5 142 Single Transfer Memory Read and Write 5 142 Single Transfer Memory Write Delayed by EWBE Signal 5 145 I O Read and Write 5 147 Single Transfer Misaligned Memory and I O Transfers 5 148 5 4 3 Burst Cycles 5 150 Burst R...

Page 8: ... Space 6 4 6 1 3 Cacheable and Noncacheable Address Spaces 6 4 6 1 4 SMM Memory Space and Cacheability 6 5 6 2 Cache 6 8 6 2 1 L2 Cache 6 9 6 2 2 Cacheability and Cache State Control 6 9 6 2 3 Writethrough vs Writeback Coherency States 6 10 6 2 4 Inquire Cycles 6 12 6 2 5 Bus Arbitration for Inquire Cycles 6 14 BUFF Arbitration 6 15 AHOLD Arbitration 6 17 HOLD Arbitration 6 19 6 2 6 Write Once Pro...

Page 9: ...nd Debug 7 1 7 1 Hardware Configuration Register HWCR 7 3 7 2 Built In Self Test BIST 7 5 7 2 1 Normal BIST 7 5 7 2 2 Test Access Port TAP BIST 7 6 7 3 Output Float Test 7 7 7 4 Cache and TLB Testing 7 7 7 4 1 Array Access Register AAR 7 8 7 4 2 Array Pointer 7 9 7 4 3 Array Test Data 7 10 7 5 Debug Registers 7 16 7 5 1 Standard Debug Functions 7 16 7 5 2 IJO Breakpoint Extension 7 16 7 5 3 Debug ...

Page 10: ... after the Cacheability of the Line is Established A 8 Comments A 9 A 3 3 Snoop Before Write Hit to ICACHE Appears on Bus A 9 A 3A Invalidations during a FLUSHIWBINVD A 9 A 3 5 Cache Line Ownership A 9 A 3 6 Write Hit to a Shared Line in the DCACHE A l0 A 4 Memory Management A ll AA l Speculative TLB Refills A ll AA 2 Page Fault Encountered by a Load Store Type of Instruction A ll A 5 Power Saving...

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Page 12: ...RE 5 13 FIGURE 5 14 I O Transfers 5 149 Burst Reads 5 152 Burst Read NA Sampled 5 153 Burst Writeback Due To Cache Line Replacement 5 156 AHOLD Initiated Inquire Miss 5 159 AHOLD Initiated Inquire Hit to Shared or Exclusive Line 5 160 AHOLD Initiated Inquire Hit to Modified Line 5 162 Basic BUFF Operation 5 164 BUFF Initiated Inquire Hit to Modified Line 5 166 HOLD Initiated Inquire Hit to Shared ...

Page 13: ...RE 6 5 FIGURE 6 6 FIGURE 6 7 FIGURE 6 8 FIGURE 6 9 FIGURE 6 10 FIGURE 7 1 FIGURE 7 2 FIGURE 7 3 FIGURE 7 4 FIGURE 7 5 FIGURE 7 6 FIGURE 7 7 FIGURE 7 8 Mode to Real Mode 5 197 Typical Desktop System BIOS Memory Map 6 3 Default SMM Memory Map 6 7 BUFF Example 6 16 AHOLD and BUFF Example 6 18 Write Once Protocol 6 21 Clock Control State Transitions 6 36 Vee and CLK 6 40 CLK Delay Function 6 41 CLK Sy...

Page 14: ... 35 TABLE 5 6 Encodings For Special Bus Cycles 5 36 TABLE 5 7 Processor to Bus Clock Ratios 5 37 TABLE 5 8 Outputs Floated When BUFF is Asserted 5 39 TABLE 5 9 MESI State Transitions for Reads 5 52 TABLE 5 10 Relation Between D63 DO BE7 BEO and DP7 DPO 5 57 TABLE 5 11 MESI State Transitions for Inquire Cycles 5 73 TABLE 5 12 Outputs Floated When HLDA is Asserted 5 76 TABLE 5 13 Interrupt Acknowled...

Page 15: ...MD5 6 Processor Technical Reference Manual 18524B O Mar1996 TABLE 7 4 Branch Trace Message Special Bus Cycle Fields 7 18 TABLE 7 5 Test Access Port TAP ID Code 7 21 TABLE 7 6 Public TAP Instructions 7 22 xiv ...

Page 16: ...A full description of the x86 programming environment is beyond the scope of this manual Instead the software sections describe differences from the 486 processor s programming environment A list of commercial books that describe the x86 pro gramming environment and other subjects of potential interest appears at the end of this preface In addition to descriptions of the AMD5K 86 processor s uniqu...

Page 17: ... as INTR are shown without an overbar Dual state signals such as R S and WBfWT have two states of assertion and therefore the term asserted has no meaning such dual state signals are driven High or Low Drive and Sample A single state signal is driven when it is asserted or negated by a logic device it is sampled when its driven state is detected by another device Cycle and Clock This term commonly...

Page 18: ...its without writing their state to any storage resource Cache Invalidation The INVD instruction invalidates the contents of the in struction and data caches without writing modified data back to memory Cache Writeback and Invalidation The WBINVD instruction writes modified lines in the data cache back to memory while invalidating each line in the in struction and data caches FLUSH Operation The FL...

Page 19: ...rm or soft reset can refer either to the assertion of RESET after power up or to the assertion of INIT System Logic Any logic outside the processor including a core logic chipset another bus master or separate controllers for L2 cache memory interrupts DMA communications video bus bridging bus arbitration or any other system function References Abel Peter IBM PC Assembly Language and Programming E...

Page 20: ...oint Arithmetic ANSIlIEEE Std 754 1985 Institute of Electrical and Electronics Engineers IEEE Standard for Radix Indepen dent Floating Point Arithmetic ANSIlIEEE Std 854 1987 Institute of Electrical and Electronics Engineers IEEE Standard Glossary of Mathe matics of Computing Terminology ANSIIIEEE Std 1084 1986 Out of print Johnson Mike Superscalar Microprocessor Design Englewood Cliffs Prentice H...

Page 21: ...486 Advanced Programming New York Van Nostrand Reinhold 1993 Slater Michael Microprocessor Based Design Englewood Cliffs Prentice Hall 1989 Stallings William Operating Systems New York Macmillan 1992 Van Gilluwe Frank The Undocumented PC Reading Addison Wesley 1994 Wakerly John F Digital Design Principles and Practices Englewood Cliffs Prentice Hall 1994 Wharton John The Complete x86 Sebastopol CA...

Page 22: ...opment and support of the popular Am386 and Am486 processors has given it a broad foundation of experi ence in the x86 architecture The AMDSK86 processor s binary compatibility with DOS and Windows compatible software running on the Pentium processor and all previous x86 proces sors has been established in extensive testing using industry standard test tools Compatibility and qualification testing...

Page 23: ...mance Execution Six execution units two ALUs two load store one branch one floating point Up to four instructions issued per processor clock Out of order issue and completion Speculative execution along three predicted branches Register renaming Data forwarding Predecoder converts x86 instructions to single cycle RISC operations ROPs Fast integer multiply 4 cycle fully pipelined Five stage pipelin...

Page 24: ...nter TSC Machine Specific Registers MSRs 4 Mbyte page size Global pages held in TLB during flushes LowPower Static 3 3 V design System Management Mode SMM with I O trapping Low power halt and stop clock states Compatible with U S Department of Energy s Energy Star program Compatible with Microsoft Advanced Power Manage ment specification Extensive Test and Debug Features Two built in self test BIS...

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Page 26: ... mem ory management Figure 2 1 shows the major logic blocks that make up the inter nal architecture The blocks are organized in the figure by stages of the processor s execution pipeline which are listed vertically on the right side of the figure The blocks are explained throughout the section that follows In this chapter the terms clock and cycle refer to processor clock cycles If bus clock cycle...

Page 27: ... i 0 J Load J Load J J Store Store J Execute J 4 Ports J J I y I I I 5 Ports r L ___ t I I I Reorder Buffer I Store J 8Ports I ROB Buffer I I 0 Result 4 Ports I t I I I Register File I Data 8 Ports I x86 GPRs FPRs J Cache J Linear Tags t Memory Management Unit TLBs and Physical Tags I J t Fastpath Hardware ROPs Bus Interface Unit MCode Microcode ROPs R S Reservation Station t64 Port 41 bits J 32 A...

Page 28: ...h the fetch logic adds the code segment base to the effective address and places the resulting linear address in the prefetch program counter which then increments as a linear address along a sequential stream All branches during prefetching are assumed to be not taken The processor predecodes its x86 instruction stream in the same clock in which x86 instructions come out of the prefetch cache An ...

Page 29: ...he sixth stage Retire may occur at a variable number of clocks after the Result stage but the Retire stage does not affect throughput performance when the processor operates in a non serialized mode which is typical of most pro cessing Thus the pipeline effectively has five stages Because the pipeline is moderately shallow penalties associated with mispredicting a branch three clocks or clearing t...

Page 30: ...erands in data cache Check protection and segment Iimit1 rward to execution units Result Fo Wr Co Dr iteto ROB rrect branch prediction ive write cycle on bus1 Retire Write to real state registers Forward from ROB Notes I Load stare instructions only AMD AMD5J1J6 Processor Technical Reference Manual I Fetch IDecode 1 I Decode 2 I Execute I Result I Retire2 J I I 2 The Retire stage may occur one or ...

Page 31: ... to be executed whether or not the branch will be taken and the cache index ofthe branch target called the successor index When the caches are invalidated all branch predictions are cleared During prefetch all branch instructions are predicted as not taken Later if the execution of a branch instruction reveals a misprediction the fetch unit backs out of the branch by invali dating all speculative ...

Page 32: ...ocessor uses a combination of hardware and microcode to convert x86 instructions into ROPs The hardware consists of four parallel jastpath converters that translate the most commonly used x86 instructions moves shifts branches ALUs into one two or three ROPs Translations requiring more than three ROPs complex instructions serializing condi tions interrupts and exceptions etc are handled by micro c...

Page 33: ...as its own FIFO reservation station with two or four entries ROPs are dispatched to reservation sta tions in program order One ROP can be dispatched to a single reservation station in a given clock thus up to four reservation stations receive an ROP each clock ROPs are issued from a res ervation station to its execution unit when all operands are available from the register file reorder buffer or ...

Page 34: ... by the reorder buffer Reservation stations are supplied with operands over eight 41 bit operand buses Execution results are sent to the reorder buffer ROB over five 41 bit result buses Tags forwarded to the execution units represent results to watch for on one of the result buses No special compiler optimizations are required for high perfor mance execution on the AMDSK 86 processor Two ALUs perf...

Page 35: ...er clock Each unit holds copies of segment descriptor fields so that it can calculate logical and linear addresses and check protection variables and segment limits Data loaded by one instruction in a load store unit can be used by another instruction in another execution unit in the next clock There is no load use penalty The data cache can be accessed in a single clock These low latencies provid...

Page 36: ...m counter associated with each instruction resolves RaP level dependencies stores speculative results provides the most recent copy of a register to execution units recovers from mispredicted branches with out altering real state and provides substitute tags to internal resources when required operands are still outstanding The x86 architecture defines only eight general purpose regis ters and eig...

Page 37: ...ed are recognized and the instruction pointer is updated For instructions that store an operand to memory retirement is the time at which the store is guaran teed to be written externally When a pipeline invalidation flush occurs it does so at the retirement stage causing all instructions in the pipeline that have not reached the retire ment stage to be invalidated The retirement stage is also cal...

Page 38: ...rformance advantage The enabling and operating modes for the caches are software controlled by the CD and NW bits of CRO When disabled both caches are locked They are accessed in all operating modes and the processor can still hit in a cache that has not been invalidated even if software has turned the caches off These mechanisms work the same on both the AMD5K 86 and Pentium processors Any area o...

Page 39: ...e 32 byte line or they can be split into two 8 byte accesses across two contiguous lines Split line fetches can provide instructions from sequential lines in a single clock This keeps decode logic supplied with a steady stream of bytes Instruction fetches can read any 16 bytes of a single line or in a split line fetch the high 8 bytes of the first line and the low 8 bytes of the next sequential li...

Page 40: ...if not to the same bank MESI cache coherency protocol maintained by physical tags Requested word first line fill protocol Pseudo random replacement policy Read write writeback or writethrough modes The data cache overcomes load store bottlenecks by support ing simultaneous accesses to two lines in a single clock if the lines are in separate banks Each of the four cache banks con tains eight bytes ...

Page 41: ...ne clock linear tag access Accesses to the instruction cache physical tags add three clocks to the one clock linear tag access Thus physical tag accesses take a total of three clocks for the data cache or four clocks for the instruction cache but they occur infrequently For write hits to the data cache how ever the additional latency for accessing the physical tags needed to determine the MESI sta...

Page 42: ...n one of the four ways for the index a line is pseudo randomly selected for replacement from one of the four ways Then the processor fills the line by driving a four transfer burst cycle on the bus aligned on 32 byte boundaries with the target quadword qword delivered first Instruction cache line fills initiate four 8 byte transfers from memory one burst cycle on the bus All 32 bytes go through th...

Page 43: ... The instruction cache implements coherency with only a valid bit which in effect works like a shared invalid subset of the MESI protocol The coherency state bits are stored in the physical tags for each cache The physical tags can be accessed by external logic using inquire cycles or the processor for internal snoops in parallel with accesses to the linear tag by programs running on the processor...

Page 44: ... modified modified writeback Write Linear invalid single write invalid invalid Miss Cache cache shared or writethrough Write shared update and exclusive4 or Write Linear single write writeback4 Hit exclusive or cache update modified writeback modified Notes 1 Linear tags are maskedbyA2OtlII physical tags are not 2 Single read single write cache update and writethrough 1to 8bytes Line fill 32 bytes...

Page 45: ...ical invalid invalid Snoop modified burst write writeback shared or exclusive FLUSH Physical invalid invalid Signal modified burst write writeback shared or exclusive WBINVD Physical invalid invalid Instruction burst write modified writeback INVD invalid invalid Instruction shared or exclusive Depends on Cache Line Replacement Physical burst write replacement line modified characteristics writebac...

Page 46: ...er which snooping occurs in the AMD5K 86 processor and the resources that are snooped All such snooping is done in the processor s physical tags in parallel with the processor s own accesses to the linear tags Thus there is no execution performance penalty for snooping In systems with multiple caching masters external logic main tains cache coherency by driving inquire cycles to the proces sor Sys...

Page 47: ...written back before invalidation 2 Ifthe snoop hits aline in the data cache store buffer or writebackbuffer the line is written back ifmodified andinvalidated Then the instruction cache readis performed again Ifthe line is modified acopy ofthe writeback data is passeddirectly to the instruction cache thus avoiding aline fillbus cycle after the writeback bus cycle 3 Ifthe snoop hits aline in the in...

Page 48: ... cache write is performed The AMD5K86 processor like the 486 processor but unlike the Pentium processor requires a jump near or far after a self modifying write to clear the prefetch cache However both the AMD5K86 and the Pentium processors require a serializing instruction after self modifying code whose physical address is aliased to multiple linear addresses Several buffers are associated with ...

Page 49: ...in which certain types of cacheable read cycles on the bus are promoted ahead of certain types of write cycles when the EWBE signal is asserted The AMDSK86 processor has no such real state write buffer between its data cache and the bus although it does implement a speculative state 4 entry 4 byte wide store buffer between the two load store execution units and the data cache The store buffer can ...

Page 50: ...rred to the data cache and it would become a writethrough going externally to main memory at the same time that it updates the data cache The processor has a l entry 32 byte wide writeback copy back buffer in the bus interface unit for replacements and invalidations The buffer is used for writebacks of modified data in the data cache due to one of the following Cache line replacement during data c...

Page 51: ...g 4 Mbyte pages Mappings to 4 Kbyte and 4 Mbyte pages can be intermixed in a given page directory the base of which is pointed to by the contents of control register 3 CR3 During memory accesses the MMU receives a linear address and searches the TLBs for a corresponding physical address If found the physical address is passed to the physical tag direc tory for a validity check If the physical addr...

Page 52: ...Read Write Reordering The processor reorders certain types of cacheable read cycles on the bus ahead of certain types of write cycles Specifically any read that hits in the instruction or data cache is promoted ahead of a write in the store buffer if the read is not from the same location to which a write in the store buffer is to be writ ten The reordering allows reads which dominate the proces s...

Page 53: ... and it alone can issue a page related excep tion TLB invalidations flushes are done in the standard ways a MOV to CR3 which loads a new page table directory or the INVLPG instruction which invalidates a single TLB entry Both the 4 Kbyte and 4 Mbyte TLBs support global pages which remain in the TLBs during such TLB invalidations when the global page extension is enabled When a TLB miss or fault oc...

Page 54: ...t during the physical tag snoop causes the cache line to be invalidated Details on software configuration for 4 Mbyte paging are given in Section 3 1 2 on page 3 5 The global page option is described in Section 3 1 3 on page 3 9 Details on the TLB stor age formats and their testing are given in Section 7 4 on page 7 7 MemoryManagement Unit MMU 2 29 ...

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Page 56: ...ut modification Because the AMD5K 86 processor takes a significantly different approach to implementing the x86 architecture some subtle differences from the Pentium processor may be visible to sys tem and code developers These differences are described in AppendixA The AMD5K 86 processor implements the following extensions to the 486 architecture 4 Mbyte Page Size Global Pages Protected Virtual E...

Page 57: ...ontrol Register 4 CR4 Extensions 31 Reserved Global Page Extension Machine Check Enable Page Size Extension Debugging Extensions Control register 4 contains bits that enable or specify many of the extensions to the 486 architecture The majority of the bits in CR4 are reserved The default state for all bits in CR4 is all zeros Figure 3 1 shows the format of CR4 Table 3 1 describes the fields in CR4...

Page 58: ... 5 for details Enables I O breakpoints in the DR7 DRO regis Debugging ters 3 DE Extensions 1 enabled 0 disabled See Section 7 5 on page 7 16 for details Selects privileged CPL O or non privileged CPL O use of the RDTSC instruction which 2 TSD Time Stamp reads the Time Stamp Counter TSC Disable 1 CPL must be 0 0 any CPL See Section 3 2 3 on page 3 27 for details Enables hardware support for interru...

Page 59: ...wing when either type of bus error occurs Latches the physical address of the failed cycle in its 64 bit machine check address register MCAR Latches the cycle definition of the failed cycle in its 64 bit machine check type register MCTR Software can read the MCAR and MCTR registers in the excep tion handling routine with the RDMSR instruction as described in Section 3 3 5 on page 3 35 The format o...

Page 60: ...sociative 4 Mbyte TLB which is separate from the 128 entry 4 Kbyte TLB From a given page directory the processor can access both 4 Kbyte pages and 4 Mbyte pages and the page sizes can be intermixed within a page directory When the Page Size Extension PSE bit in CR4 is set the processor translates linear addresses using either the 4 Kbyte TLB or the 4 Mbyte TLB depending on the state of the page si...

Page 61: ...byte paging option 1 Set the Page Size Extension PSE bit in CR4 to 1 2 Set the Page Size PS bit in the page directory entry to 1 3 Write the physical base addresses of 4 Mbyte pages in bits 31 22 of page directory entries Bits 21 12 of these entries must be cleared to 0 or the processor will generate a page fault 4 Load CR3 with the base address of the page directory that contains these page direc...

Page 62: ...ry in a 4 Kbyte page table in memory whose physical base address is specified by bits 31 22 of the page directory entry Bits 11 0 of the linear address select a byte in a 4 Kbyte page whose physical base address is specified by the page table entry 4 Mbyte Paging Figure 3 3 Bits 31 22 of the linear address select an entry in a 4 Mbyte page directory in mem ory whose physical base address is stored...

Page 63: ... Dirty For 4 Mbyte pages the processor sets this bit to 1 during a write to the page that is mapped by this page directory entry o not written 1 written The processor sets this bit to 1 during a read or 5 A Accessed write to any page that is mapped by this page directory entry o not read or written 1 read or written Specifies cacheability for all pages mapped by this Page Cache Dis page directory ...

Page 64: ...e operating system code and data pages that are always required The processor operates faster if these entries are retained across task switches and procedure calls To specify individual pages as global 1 Set the Global Page Extension GPE bit in CR4 2 Optional Set the Page Size Extension PSE bit in CR4 3 Set the relevant Global G bit for that page For 4 Kbyte pages Set the G bit in both the page d...

Page 65: ... If 17 p Physical Base Address V L Available to Software AVL 11 9 I I I I I Global G 8 Page Size 0 PS 7 Dirty D 6 Accessed A 5 Page Cache Disable PCD 4 Page Writethrough PWT 3 User Supervisor U S 2 Write Read W R 1 Present valid P 0 FIGURE 3 5 Page Table Entry PTE 3 10 Software Environment and Extensions ...

Page 66: ...is page table entry o not written 1 written The processor sets this bit to 1 during a read or 5 A Accessed write to any page that is mapped by this page table entry o not read or written 1 read or written Specifies cacheability for all locations in the page Page Cache mapped by this page table entry Whether a loca 4 PCD tion is actually cached also depends on several Disable other factors o cachea...

Page 67: ...the operating system controls Virtual 8086 mode access to the IF flag by trapping instructions that can read or write this flag These instructions include ST CLI PUSHF POPF INTn and IRET This method prevents changes to the real IF when the I O privilege level IOPL in EFLAGS is less than 3 the privilege level at which all Virtual 8086 tasks run The operating system maintains an image of the IF flag...

Page 68: ... enabled the IF modifying instruc tions that are normally trapped by the operating system are allowed to execute but they write and read the VIF bit rather than the IF bit in EFLAGS This leaves maskable interrupts enabled for detection by the operating system It also indicates to the operating system whether the Virtual 8086 program is able to or expecting to receive interrupts When an external in...

Page 69: ...occurs for a Virtual 8086 program who s VIF bit is cleared The bit is checked by the processor when the program sub sequently attempts to set VIF Figure 3 6 and Table 3 4 show the VIF and VIP bits in the EFLAGS register The VME extensions support conventional emulation methods for passing interrupts to Virtual 8086 pro grams but they make it possible for the operating system to avoid time consumin...

Page 70: ...GS Register TABLE 3 4 Virtual Interrupt Additions to EFLAGS Register Bit Mnemonic Description Function Set by the operating system via the EFLAGS image on the stack when an external maskable 20 VIP Virtual Interrupt interrupt INTR occurs for a Virtual 8086 pro Pending gram who s VIF bit is cleared The bit is checked by the processor when the program subsequently attempts to set VIF When the VME bi...

Page 71: ...PL I O Privilege Level bits in EFLAGS bits 13 12 GP O General protection exception with error code 0 IF Interrupt Flag bit in EFLAGS bit 9 VIF Virtual Interrupt Flag bit in EFLAGS bit 19 TABLE 3 5 Instructions that Modify the IF or VIF Flags Mode TYPE PE VM VME PVI IOPL GP O IF VIF CLI 0 0 0 0 No IF f 0 STI 0 0 0 0 No IF f l PUSHF 0 0 0 0 No No Change Real Model IF f POPF 0 0 0 0 No Stack Image IF...

Page 72: ...f 1 STI 1 0 0 0 CPL Yes No Change PUSHF 1 0 0 0 CPL No No Change PUSHF 1 0 0 0 CPL No No Change 286 Protected Mode IF f POPF 1 0 0 0 CPL No Stack Image POPF 1 0 0 0 CPL No No Change IF f IRET 1 0 0 0 CPL No Stack Image IF f IRET 1 0 0 0 CPL No Stack Image Notes I All Virtual 8086 tasks run at CPL 3 2 INTn handlers and IRETO instructions run at CPL o CP O ifan attempt is mode to set VIF when VIP I ...

Page 73: ... IF f 1 STI 1 1 0 CPL Yes No Change PUSHF 1 1 0 CPL No No Change PUSHF 1 1 0 CPL Yes No 386 Virtual Change 8086 Model IF f POPF 1 1 0 CPL No Stack Image POPF 1 1 0 CPL Yes No Change IF f IRETD 1 1 0 CPL No Stack Image IRETD 1 1 0 CPL Yes No Change Notes I All Virtual BOB6 tasks run at PL 3 2 INTn handlers and IRETO instrudions run at PL O CP O ifan attempt is made to set VIFwhen VIP I Not applicab...

Page 74: ...hed into stack IF PUSHFD 1 1 1 3 No Pushed Pushed Virtual 8086 Mode PUSHFD 1 1 1 0 Yes Extensions POPF 1 1 1 3 No Popped Not VME 1 2 Popped Not Popped POPF 1 1 1 0 No Popped from stack IF POPFD 1 1 1 3 No Popped Not Popped POPFD 1 1 1 0 Yes IF f VIFf IRETD 1 1 1 3 No Return Return Stack Stack Image Image IF f VIFf IRETD 1 1 1 0 No Return Return Stack Stack Image Image Notes I All Virtual 8086 task...

Page 75: ...PUSHFD 1 0 1 3 No Pushed Pushed Protected PUSHFD 1 0 1 0 No Pushed Pushed Virtual Not Extensions POPF 1 0 1 3 No Popped Popped PVI 1 2 Not Not POPF 1 0 1 0 No Popped Popped POPFD 1 0 1 3 No Popped Not Popped POPFD 1 0 1 0 No Not Not Popped Popped IF VIF IRETD 1 0 1 3 No Return Return Stack Stack Image Image IF VIF IRETD 1 0 1 0 No Return Return Stack Stack Image Image Notes I All Virtual 8086 task...

Page 76: ...Bitmap near the top The IRB contains 256 bits one for each possible software interrupt vector The most sig nificant bit of the IRB is located immediately below the base of the IOPB This bit controls interrupt vector 255 The least sig nificant bit of the IRB controls interrupt vector O The bits in the IRB work as follows Set If set to 1 the INTn instruction behaves as if the VME extensions are not ...

Page 77: ...System Data Structure Base Address of 10PB aOOah OOaah aOOOh OOoah aOOOh aOOah aOOah ED ESI EBP ESP EBX EDX ECX EAX EFLAGS EIP CR3 aooah ESP2 aOOah ESP OOaah ESpa aooah lOT Selector GS FS DS 55 CS ES 552 55 ssa a j TSSLimit fromTR 1T 64h 18524B O Mar1996 aaaah Link Prior TSS Selector a FIGURE 3 7 Task State Segment TSS J 22 Software Environment andExtensions ...

Page 78: ...Inter rupt Redirection Bitmap IRB in the tasks TSS GP O General protection exception with error code 0 IDT Protected Mode Interrupt Descriptor Table IVT Real and Virtual 8086 Mode Interrupt Vector Table TABLE 3 6 Interrupt Behavior and Interrupt Table Access Mode Interrupt PE VM VME PVI IOPL IRB GP O IDT IVT Type Real mode Software 0 0 0 0 3 Hardware 0 0 0 0 3 Software 1 0 0 3 286 Pro Hardware 1 0...

Page 79: ...E When a program is executed at CPL 3 it can set and clear its copy of the VIF flag without causing gen eral protection exceptions The only differences between the VME and PVI extensions are that in PVI selective INTn interception using the Interrupt Redirection Bitmap in the TSS does not apply and only the STI and CLI instructions are affected by the extension Tables 3 5 and 3 6 show among other ...

Page 80: ...hine Check Address Register MCAR The processor latches the address of the current bus cycle in its 64 bit Machine Check Address Register MCAR when a bus cycle error occurs These errors are indicated either by a system logic asserting BUSCHK or b the processor asserting PCHK while system logic asserts PEN The MCAR can be read with the RDMSR instruction when the ECX register contains the value OOh F...

Page 81: ...m logic asserting BUSCHK or b the proces sor asserting PCHK while system logic asserts PEN The MCTR can be read with the RDMSR instruction when the ECX register contains the value 01h Figure 3 9 and Table 3 7 show the formats of the MCTR register The contents of the register can be read with the RDMSR instruction The proces sor clears the CHK bit bit 0 in MCTR when the register is read with the RD...

Page 82: ...ter can be written or read using the WRMSR or RDMSR instructions when the ECX register contains the value lOh and CPL O The counter can also be read using the RDTSC instruction see Section 3 3 4 on page 3 34 but the required privilege level for this instruction is determined by the Time Stamp Disable TSD bit in CR4 With any of these instruc tions the EDX and EAX registers hold the upper and lower ...

Page 83: ...R can be written or read with the WRMSR or RDMSR instruction when the ECX register contains the value 83h For details on the HWCR see Section 7 1 on page 7 3 3 3 New Instructions 3 28 In addition to supporting all of the 486 processor instructions the AMDSK 86 processor implements the following instructions CPUID CMPXCHG8B MOV to and from CR4 RDTSC RDMSR WRMSR RSM Illegal instruction reserved opco...

Page 84: ...plements the ID flag bit 21 in the EFLAGS register By writing and reading this bit software can verify that the processor will execute the CPUID instruction If 0 is written to EAX the following values are returned in EAX EBX ECX and EDX EAX 00000001h EBX 68747541h ECX 444D4163h EDX 69746E65h These values decode to the ASCII string AuthenticAMD when read in the EBX EDX ECX registers in least signif...

Page 85: ...following pseudo code illustrates the use of the CPUID instruction begin if vendor string report desired load EAX with Oh execute cpuro instruction opcode OFh OA2h Result EBX Auth EOX enti ECX cAMO else if CPU information desired 3 30 load EAX with 1 execute CPUIO instruction opcode OFh OA2h Result EAX 3 0 stepping IO contact AMO for specifics EAX 7 4 Model AMO SSA5 processor OOOOb AM05K 86 proces...

Page 86: ...es K86 Model Specific Registers EDX 6 Ob Reserved EDX 7 Support of machine check exception bit 7 1 indicates support EDX 8 Support of CMPXCHG8B instruction bit 8 1 indicates support EDX 9 Support of global paging extension bit 9 1 indicates support EDX 31 10 Reserved end New Instructions 3 31 ...

Page 87: ...ual 8086 mode Page fault The CMPXCHG8B instruction is an 8 byte version of the 4 byte CMPXCHG instruc tion supported by the 486 processor CMPXCHG8B compares a value from memory with a value in the EDX and EAX register as follows EDX Upper 32 bits of compare value EAX Lower 32 bits of compare value If the memory value matches the value in EDX and EAX the ZF flag is set to 1 and the 8 byte value in ...

Page 88: ... Registers Affected Flags Affected Exceptions Generated opcode OF22 OF20 CPL O description Move to CR4 from register Move to register from CR4 CR4 32 bit general purpose register none Real mode none Virtual 8086 mode GP o Protected mode GP O if CPL not 0 These instructions read and write control register 4 CR4 New Instructions J Jl ...

Page 89: ...RDTSC instruction can be used to read the counter at privilege levels higher than CPL O The required privilege level for using the RDTSC instruction is determined by the Time Stamp Disable TSD bit in CR4 as follows CPL O Set the TSD bit in CR4 to 1 Any CPL Clear the TSD bit in CR4 to 0 The RDTSC instruction reads the counter value into the EDX and EAX registers as follows EDX Upper 32 bits of TSC ...

Page 90: ...HK or PCHK signal was asserted For details see Section 3 1 1 on page 3 4 01h Machine Check Type Register MCTR This contains the cycle definition of the last bus cycle for which the BUSCHK or PCHK signal was asserted For details see Section 3 1 1 on page 3 4 The processor clears the CHK bit bit 0 in MCTR when the register is read with the RDMSR instruction 10h Time Stamp Counter TSC This contains a...

Page 91: ...his contains the data to be read writ ten All MSRs are 64 bits wide However the upper 32 bits of the AAR are write only and are not returned on a read EDX remains unaltered making it more convenient to maintain the array pointer If an attempt is made to execute either the RDMSR or WRMSR instruction when CPL is greater than 0 or to access an undefined model specific register the proces sor generate...

Page 92: ...ion should be the last instruction in any System Management Mode SMM service routine It restores the processor state that was saved when the sm interrupt was asserted This instruction is only valid when the processor is in SMM It generates an invalid opcode exception at all other times The processor enters the Shutdown state if any of the following illegal conditions are encountered during the exe...

Page 93: ...Generated opcode OFFF none none none description Illegal instruction reserved opcode Real Virtual 8086 mode Invalid opcode Protected mode Invalid opcode Protected mode Invalid opcode 18524BjO Marl 996 This opcode always generates an invalid opcode exception The opcode will not be used in future AMD K86 processors J J8 Software Environment andExtensions ...

Page 94: ...mmon to both the AMD5K86 and Pentium processors and techniques specific to the AMD5K86 processor In general all optimization techniques used for the Pentium processor apply to any wide issue x86 processor but wider issue designs like the AMD5K 86 processor have fewer restrictions 4 1 1 General Superscalar Techniques Code Optimization Short Forms Use shorter forms of instructions to increase the ef...

Page 95: ...cted branches have no cost mispredicted branches incur a three clock penalty Stack References Use ESP for references to the stack so that EBP remains available for general use Stack Allocation When placing outgoing parameters on the stack allocate space by adjusting the stack pointer prefer ably at the same time local storage is allocated on proce dure entry and use moves rather than pushes This m...

Page 96: ... pipelined at one per cycle with 4 cycle latency in contrast to the Pentium processor s serialized 9 cycle time MUL has the same latency although the implicit AX usage of MUL prevents independent parallel MUL operations Dispatch Conflicts Load balancing that is selecting instructions for parallel decode is still important but to a lesser extent than on the Pentium processor In particular arrange i...

Page 97: ... operations ALD branch load store in parallel with floating point operations Locating Branch Targets Performance can be sensitive to code alignment especially in tight loops Locating branch targets to the first 17 bytes of the 32 byte cache line maxi mizes the opportunity for parallel execution at the target NOPs can be added to adjust this alignment The AMD5K 86 processor executes NOPs opcode 90h...

Page 98: ... instructions The first column in these tables indicates the instruction mnemonic and operand types The fol lowing notations are used in the AMD5K86 microprocessor doc umentation reg register mem memory location imm immediate value inC16 16 bit integer inC32 32 bit integer inC64 64 bit integer reaC32 32 bit floating point number reaC64 64 bit floating point number reaCBO 80 bit floating point numb...

Page 99: ... decode stage at the same time If a microcoded instruction appears at the head of the byte queue without having been present in the queue on the previous cycle there is a one cycle penalty for MROM entry point generation Each x86 instruction is converted into one or more ROPs The fourth column shows the execution unit and timing for each of the ROPs The ROP types and corresponding execution units ...

Page 100: ...le in which the result is returned on the result bus It is indicated only when the latency is greater than one cycle For stores it reflects the relative time that a store operand is available to be for warded from the store buffer to a dependent load opera tion Using the time that the first Rap of an instruction is dis patched to an execution unit as clock 1 the x y value indicates in which clock ...

Page 101: ...g ADD reg mem ADD mem reg ADD ALiAXIEAX imm ADD reg imm ADDmem imm AND reg reg AND reg mem ANDmem reg AND ALiAXIEAX imm AND reg imm ANDmem imm BSF reg reg BSFreg mem BSR reg reg BSRreg mem BSWAPreg BT reg reg 4 8 Fastpath or Microcode F F F F F F F F F F F F F F F F F F Execution Unit Timing alu 1 1 ld 111 alu 1 2 ld 111 alu 112 st 1 1 3 alu 111 alu 1 1 ld 111 alu 1 2 st 11113 alu 111 ld 111 alu 1...

Page 102: ...mm BTS reg reg BTS mem reg BTS reg imm Dispatch and Execution Timing Fastpath or Microcode M F F F M F F F M F F F M F Execution Unit Timing alul 1 1 alu 112 alu 2 3 Id 2 4 alul 3 5 alul 1 1 Id alul alul alul alu alu Id alul st alul Id alul st alul alul alu alu Id alul st alul Id alul st alul alul alu alu Id alul st alul 111 1 2 1 1 1 1 1 2 2 3 2 4 3 5 3 5 6 111 1 1 112 1 1 3 1 1 111 1 2 2 3 2 4 3...

Page 103: ...m IMUL AX AL reg IMUL EDX EAX EAX reg IMUL reg reg 4 10 Fastpath or Microcode F M M M F F F F F F F F F F F F F F 18524B O Mar1996 Execution Unit Timing ld alul st alu st alu brn alu st alu brn alu ld st alu brn alul alu ld alu ld alu alu alu ld alu alul alu alu ld alu st fpfill fmul fpfill fmul fpfill fmul 1 1 1 2 1 113 1 1 1 1 2 1 1 111 1 1 11112 111 1 1 111 111 1 1 2 111 2 2 111 111 1 1 112 1 1...

Page 104: ...g JMPmem LEA LOOP short displacement LOOPE short displacement LOOPNE short displacement MOVreg reg MOVreg mem MOVmem reg Dispatch andExecution Timing Fastpath or Microcode F F F F F F F F F F F F F F F F F M M F F F Execution Unit Timing fpfill 111 4 fmul 11114 ld 111 fpfill 1 2 4 fmul 1 2 4 ld 1 1 fpfill 1 2 4 fmul 1 2 4 ld 1 1 fpfill 1 2 4 fmul 1 2 4 ld fpfill fmul alu alu ld alu st brn brn brn ...

Page 105: ... EAX reg MUL AX AL mem MUL EDX EAX EAX mem NEG reg NEGmem NOP XCHG EAX EAX NOT reg NOTmem OR reg reg 4 12 Fastpath or Microcode F F F F F F F F F F F F F F F F F F F F F 18524B O Mar1996 Execution Unit Timing ld 1 1 st 1 2 3 ld 1 1 st 1 1 alu 1 1 alu 111 alu 111 st 1 1 alu 1 1 ld 1 1 st 112 3 alul 1 1 ld 1 1 alul 1 2 alu 1 1 ld 1 1 alu 1 2 fpfiIl 1 114 fmul 1 114 fpfiIl 1 1 4 fmul 1 1 4 ld 1 1 fpf...

Page 106: ...eg POPmem PUSH reg PUSH reg PUSHimm PUSHmem RET near RET near imm ROLreg 1 ROLmem l Dispatch and Execution Timing F F F F F F F M F F F M F M F F Id 111 alu 1 2 Id 111 alu 112 5t 1 1 3 alu 111 alu 1 1 Id 111 alu 112 5t 1 1 3 Id 111 alu 111 Id 111 alu 1 1 Id 111 Id 1 1 5t 2 2 3 alu 2 2 5t 111 alu 1 112 5t 111 alu 1 1 2 alu 1 1 5t 1 1 2 alu 111 Id 1 1 st 1 1 2 alu 1 1 Id 1 1 alu 1 1 brn 1 2 Id 1 1 a...

Page 107: ...eg CL SARmem CL SETcc reg SETccmem SHL reg 1 4 14 Fastpath or Microcode F F F F F F F F F F F F F F F F F F F 18524B O Mar1996 Execution Unit Timing alu1 1 1 ld 1 1 alu1 1 2 st 1 113 alu1 1 1 ld 1 1 alu1 1 2 st 1 1 3 alu1 1 1 ld 1 1 alu1 1 2 st 1 1 3 alu1 111 ld 1 1 alu1 1 2 st 1 1 3 alu1 1 1 ld 111 alu1 1 2 st 11113 alu1 1 1 ld 1 1 alu1 1 2 st 1 1 3 alu1 1 1 ld 1 1 alu1 1 2 st 1 1 3 alu1 111 ld 1...

Page 108: ...reg mem SHRmem imm SHRreg CL SHRmem CL SHRD reg reg imm Dispatch and Execution Timing Fastpath or Microcode F F F F F F M F M F F F F F F F Execution Unit Timing ld 1 1 alul 112 st 1 1 3 alul ld alul st alul ld alul st alul alul alul ld alul st alul alul alul ld alul st alul ld alul st alul ld alul st alul ld alul st alul alul 111 111 112 1 113 111 1 1 1 2 1 1 3 1 1 2 2 111 1 1 2 2 2 2 3 1 1 2 2 1...

Page 109: ... TEST AL AX EAX imm TEST mem imm XCHG reg reg XCHG mem reg XOR reg reg 4 16 Fastpath or Microcode M F M F F F F F F F F F F F F F F F 18524B O Mar1996 Execution Unit Timing alu1 1 1 ld 1 1 alu1 2 2 st 2 2 3 alu1 1 1 alu1 2 2 alu1 1 1 ld 1 1 alu1 2 2 st 2 2 3 alu 1 1 ld 1 1 alu 1 2 ld 1 1 alu 1 2 st 1 1 3 alu 1 1 alu 1 1 ld 111 alu 1 2 st 1 1 3 alu 1 1 ld 111 alu 112 alu 1 1 alu 1 1 ld 1 1 alu 1 2 ...

Page 110: ...he rate of one every 3 cycles In this example the array size is a constant The loop is unrolled to perform sepa rate MAC operations in parallel for even and odd elements The final sum is generated outside the loop as well as the final iteration for odd sized arrays mac_loop MOV EAX ESI ECX 4 MOV EBX ESI ECX 4 4 IMUL EAX EDI ECX 4 IMUL EBX EDI ECX 4 4 ADD ECX 2 ADD EDX EAX ADD EBP EBX CMP ECX EVEN_...

Page 111: ...ger Dot Produd Internal Operations Timing Instruction IMUL EAX EDIHECX 4 4 Notes L load execute M multiplyexecute A ALU execute 8 branch execute result retire update realstate preceding execute waiting in the reservation station 4 18 18524B O Mar1996 Performance ...

Page 112: ...g load store ALU If data is being forwarded from the FPU itself however no format con version is required and operands are fast forwarded from the back end of a pipe to the front of any other pipe without the one cycle delay The add subtract reverse FPU latencies assume that cancella tion does not occur in the adder subtractor If cancellation does occur an extra cycle is required to normalize the ...

Page 113: ... F F M F M M M 18524BjO Mar1996 Execution Unit Timing fpfill 112 5 fadd 1 2 5 fpfill 1 2 4 fchs 112 4 fpfill 1 2 4 fcmpst 112 4 Id 1 1 fpfill 1 3 5 fmv 1 3 5 Id Id fpfill fadd fpfill fmv alu 1 1 1 2 1 4 6 1 4 6 1 2 4 1 2 4 111 Id 1 1 fpfill 113 5 fmv 1 3 5 Id Id fpfill fadd fpfill fmv nop alu alu Id fpfill fadd fpfill fadd Id fpfill fadd fpfill fadd 1 1 1 2 1 4 6 11416 1 2 4 1 2 4 11112 11112 1 1 ...

Page 114: ... M M M F F M M M Execution Unit Timing Id 1 1 fpfill 1 3 7 fadd 1 3 7 fpfill 2 7 9 fmv 2 7 9 Id fpfill fadd fpfill fmv Id fpfill fadd fpfill fmv Id fpfill fadd fpfill fmv 1 1 113 7 1 3 7 2 7 9 2 7 9 1 1 1 3 7 1 3 7 2 7 9 2 7 9 1 1 1 3 7 113 7 2 7 9 2 7 9 Id 1 1 fpfill 113 7 fadd 1 3 7 Id 1 1 fpfill 1 3 7 fadd 1 3 7 Id 1 1 Id 1 2 fpfill 1 4 8 fadd 114 8 Id 111 fpfill 1 3 7 fadd 1 3 7 fpfill 2 7 11 ...

Page 115: ...d M M M M M M M M 18524BjO Mar1996 Execution Unit Timing ld fpfill fadd st ld fpfill fadd st ld fpfill fadd st ld fpfill fadd st ld ld fpfill fadd st st ld fpfill fadd fpfill fadd ld fpfill fadd fpfill fadd Id fpfill fadd fpfill fadd 1 1 112 5 112 5 11516 111 112 5 112 5 115 6 111 11215 112 5 11516 111 112 5 112 5 1 5 6 111 112 11215 112 5 2 3 6 2 417 111 11317 113 7 2 7 10 2 7 10 1 1 1 3 7 11317 ...

Page 116: ...g Fastpath or Microcoded M F M M F F F F M F F F F Execution Unit Timing Id fpfill fadd fpfill fadd Id fpfiil fmv Id Id fpfill fmv Id Id fpfill fmv 111 1 317 1 3 7 2 7 10 217110 111 1 3 5 1 3 5 111 1 2 1 4 6 1 4 6 111 1 2 1 6 8 11618 fpfill 1 2 4 fmv 1 2 4 nop 1 1 fpfill 112 8 fmul 1 2 8 fpfill fmul Id fpfill fmul 112 8 112 8 111 113 7 113 7 Id 111 Id 1 2 fpfill 1 4 10 fmul 1 4 10 fpfill 1 2 8 fmu...

Page 117: ...F M F 18524B O Marl 996 Execution Unit Timing fpfiIl 1 2 8 fadd 1 2 8 ld 1 1 fpfiIl 1 2 4 fmv 112 4 st 112 5 fpfiIl 112 4 fmv 1 2 4 ld fpfiIl fmv st ld ld fpfiIl fmv st st ld ld fpfiIl fmv st st 1 1 1 2 4 1 2 4 1 2 5 111 1 2 1 2 4 1 2 4 2 3 5 2 4 6 1 1 1 2 1 2 4 112 4 2 3 5 2 4 6 fpfiIl 112 4 fmv 112 4 fpfiIl fadd fpfiIl fadd ld fpfiIl fadd ld ld fpfiIl fadd fpfiIl fadd 112 5 1 2 5 1 2 5 1 2 5 1 1...

Page 118: ...atch and Execution Timing Fastpath or Microcoded F F F M F F F F F F F F M Execution Unit Timing fpfill 1 2 5 fadd 112 5 fpfill 1 2 5 fadd 1 2 5 Id 1 1 fpfill 1 3 6 fadd 113 6 Id 111 Id 1 2 fpfill 1 4 7 fadd 1 417 fpfill fadd fpfill fmv 112 5 112 5 112 4 112 4 fpfill 1 2 4 fmv 11214 fpfill 1 2 4 fmv 11214 nap 111 fpfill 1 2 4 fmv 11214 nap 111 alu 1 1 fpfill 1 2 4 fmv 11214 brn fpfill fmv fpfill f...

Page 119: ......

Page 120: ...the architectural characteristics and functions of the signals and bus cycles The processor data sheet defines the setup and hold times for signals Throughout this chapter unless otherwise stated the term clock refers to bus clock eLK cycles not processor clock cycles The term cycle refers to bus cycles not clock cycles The terms asserted and negated mean that a signal is sampled asserted or sampl...

Page 121: ...s Figure 5 1 Signal Groups summarizes the processor s sig nals showing the functional groups to which each signal belongs the same figure appears in the introduction to this manual Table 5 1 Summary of Signal Characteristics shows each signal s 110 type when it is sampled driven and floated and its internal resistor if any Table 5 2 on page 5 9 Conditions for Driving and Sampling Signals shows the...

Page 122: ... Inquire Address AIJSC Fl1TIVl Cycles Parity l iJlffiR INV BEl NO D C AMD5K86 FERR EWIlt Processor Floating Point Cycle OCR lGf JNE Errors Definition M Kl and N7i Control sevc W R IlIJSLRK flIJSF INIT LAmE INTR External NMI Interrupts KEN Cache PRDY Interrupt Control PCD R S Acknowledge PWT RESET and Reset WB wr SMJ 5M1ACT STPa K FRDVfC ERR TCK TDI TDO TMS TRST Test and Debug FIGURE 5 1 Signal Gro...

Page 123: ...e bus cycle HLDA BF I Falling edge of RESET pullup BUFF I Every clock BRDY I Every clock from one clock after ADS until the last expected BRDY of the bus cycle BRDYC I same as BRDY pullup First clock of every bus cycle same as ADS cache store cache tag recovery and BREQ 0 aliased cache load Asserted continuously while processor is held off bus and needs access to continue BUSCHK Every BRDY Recogni...

Page 124: ...fter the assertion of HLDA except while the proces sor drives A31 A3 while it asserts HITl l and one clock after EAUS With BRDY of external write cycles and in EWBE I every clock thereafter until EWBE is asserted FERR 0 Every clock Every clock Falling edge triggered Recog nized at next instruction boundary FLuSHl I Acknowledged with Flush Acknowledge spe cial bus cycle FRCMCl I Every clock in whic...

Page 125: ...s first Recognized only during read cycles From ADS until last expected BRDY of the r ucK 0 bus cycle Negated for one clock dead BOFF 1 or cycle between sequential locked opera HLDA tions MJID 0 From ADS until last expected BRDY of the BOFF 1 or bus cycle HLDA From one clock after ADS until the first NA I expected BRDY of a bus cycle The only function of NA is to validate KEN or WBI WT in place of...

Page 126: ...cog SlVITl I nized at next instruction boundary pullup Acknowledged with SMIACT From one clock after the last expected BRDY of the bus cycle while EWBE is SMIACt 0 asserted until the return from SMM inter rupt handler Every clock Level sensitive Recognized at STpCLKl I next instruction boundary Acknowledged pullup with Stop Grant special bus cycle TCK I Always pullup TDI I Every rising TCK edge du...

Page 127: ...edactive Alloutputsandbidirectionalsare floatedduring the float test FITfSR at RESET Conditions for Driving and Sampling Signals Table 5 2 shows the processor states signal states and bus cycles during which the processor can drive or sample each sig nal The table indicates when signals can be driven or sampled so that their state has some practical meaningful effect on the state of the processor ...

Page 128: ...ly driven or sampled Bus Cycles or Cache Accesses38 Arbitration States and Modes8 Reset Debug Signal 11 1 V 0 0 l l 11 1 11 1 11 1 r CIJ CIJ en CIJ CIJ CIJ CIJ CIJ CIJ U 0 CIJ t CIJ 0 s Q S 11 1 S r E 8 2 CIJ C s J C t U 0 0 C 0 C CIJ 0 75 l 0 Q U CIJ S I C 0 I C r 5 u 0 0 0 UJ J J CIJ CIJ 0 l V l 0 c o 0 0 I I r rc 0 0 w 0 U C t t 0 I V V V V a Signal Overview 5 9 ...

Page 129: ...AD57 HIT 0 RITI if 0 INV FERR TGf 1NE 5 10 Conditions under which signals are meaningfully driven or sampled Bus Cycles or Cache Accesses38 Arbitration v v C VI VI ra Q Q Q s u eo Q VI z Q U C a a Q Q E E r S Q Q u c O u 2E 2E ra 5 a u a VI s J Q 8 8 0 0 C C t6 l C 0 0 Q 0 0 I n 5 C z Cache Control States and Modes8 Q s s u 3 ra a a Q 0 E 0 0 l r ra a s n z v n 8 C I LoU n LoU eo Reset Debug 8 C J...

Page 130: ...d Sampling Signals continued Conditions under which signals are meaningfully driven or sampled Bus Cycles or Cache Accesses38 Arbitration States and Modes8 Signal s 0 CIJ II l II l c CIJ CIJ lI CIJ 0 0 lI 8 8 c u C ttl 0 C Cl C C u ti i 0 Cl 0 V 9 LU I V 0 Signal Overview Reset Debug C 8 C Cl 0 0 5 11 ...

Page 131: ... locked cycles 14 Includes Protected Virtual BOB6 andRealmodes unless otherwise indicated 15 During the Hardware Debug Tool HOT mode this signalis onlymeaningful for cache write misses PWT O and WBjWT l tran sition asharedline to an exclusiveline The signalisnotmeaningfulduring cachereadmissesin the HOTmode because the caches are never filled during the HOTmode 16 Sampledordriven onlyduring the co...

Page 132: ...practical effect is to assert HLDA 36 Writebacks or writethroughs cannot occur when HLDA is asserted 37 During writebacks 38 During writebacks or writethroughs 39 Including writebacks and writethroughs except for HLDA 40 The processor cannot drive the interrupt acknowledge cycle and therefore cannot obtain the interrupt vector 47 IfRJJ5R is asserted while AHOLD 7IDFF or HLDA is asserted the outcom...

Page 133: ... only the following definitions Interrupt The assertion or in the case of R1S the driving Low of one of eight hardware input signals BUSCHK RiS FLOSH SMI INIT NMI INTR or STPCLK Exception Any software initiated event that accesses an entry in the Real mode interrupt vector table IVT or in the Protected mode interrupt descriptor table IDT External Interrupt Same as interrupt Software Interrupt In R...

Page 134: ...uch interrupts The processor performs an interrupt by executing a microcode routine In this sense an interrupt acts like the execution of a complex instruction and the microcode routine has a comple tion boundary that acts like an instruction retirement bound ary In effect the microcode routine for an interrupt begins executing when the interrupt is recognized on an instruction boundary and it fin...

Page 135: ...ting another debug fault Table 5 3 shows the characteristics of interrupts and excep tions and the priority with which the processor recognizes them The term priority means two things here Simultaneous Interrupts The order in which a single inter rupt or exception is selected for recognition if all occur simultaneously and Latched Interrupts The order in which latched interrupts any of the four ed...

Page 136: ...rs do not change ferogram flow instead they simplypause program flow for the duration ofthe interrupt fundion and then return to where they eft off Ifthe machine check enable MCE bit in CR4 is set to 1 The entry point for the 5Ml interrupthandler is at offset BOOOh from the 5MM Bose Address Only the edge triggered interrupts are latched when asserted Allinterrupts are recognized at the nextinstruc...

Page 137: ...ffected Bus Signal Compatibility with Pentium Processor The differences in bus signal functions between the AMD5K86 and Pentium processors are described in Section A l on page A 2 5 2 Signal Descriptions 5 18 The following pages describe each signal in detail The bus cycle protocols that use these signals are described in Section 5 3 on page 5 137 Chapter 6 describes the context in which the SMM a...

Page 138: ...es The action of clearing A20 so that addresses above 1MB wrap around to addresses below 1 Mbyte simulates the behavior of the 8086 processor allowing the processor to run software designed for DOS A 2UM should only be asserted when the pro cessor runs in Real mode A 2UM should not be asserted during the first code fetch follow ing the RESET or INIT cycles because the masking of bit 20 leads to a ...

Page 139: ...he line fills caused by read misses cache writethroughs caused by write misses or write hits to lines in the shared state and cache accesses that occur while the processor does not control the bus However AmM does not mask writebacks or invalidations caused by internal snoops inquire cycles the FLUsH signal or the WBINVD instruction such addresses are looked up only in the physical tags which are ...

Page 140: ...on they do not provide an address The processor floats A31 A3 as outputs one clock after system logic asserts AHOLD or BUFF and in the same clock that the processor asserts HLDA As Inputs While AHOLD BUFF or HLDA is asserted the pro cessor samples A31 AS in the same clock as EAUS A31 A5 are sampled in this way during inquire cycles in the normal operat ing modes Real Protected and Virtual 8086 and...

Page 141: ...s at 32 byte aligned addresses address of the first quadword is xxxx_xxOOh Thus A4 A3 are always OOb for writebacks TABLE 5 4 Address Generation Sequence During Bursts Address Driven By Address of Subsequent Quadwords1 Processor on A31 A3 Generated By System Logic Quadword 1 Quadword 2 Quadword 3 Quadword4 OOh 08h IOh 18h 08h OOh 18h IOh IOh 18h OOh 08h 18h IOh 08h OOh Notes 1 quadword 8 bytes Sys...

Page 142: ... must be interpreted by system logic in con junction with the A2UM input The processor does not control the complete bus during a writeback caused by an inquire cycle in these cases AHOLD BUFF or HOLD may still be asserted However in addition to writebacks caused by inquire cycle hits writebacks can also occur while the processor controls the bus by processor initi ated cache line replacements int...

Page 143: ... the falling edge of RESET the states of BRDYC and BUs CHI control the drive strength on A21 A3 not including A31 A22 The drive strength is weak for all states of BRDYC and BUSCHK except BRDYC and BUSCHK both Low 0 in which case the drive strength is strong The A31 A22 signals use the weak drive strength at all times See the data sheet for details Unlike the Pentium processor pipelined address dat...

Page 144: ... spe cial bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM or while PRDY is asserted While AHOLD is asserted and during the Shutdown Halt and Stop Grant states A DS is driven only for writebacks that result from inquire cycle hits A DS is not driven during the Stop Clock state or while BUFF HLDA RESET or INIT is asserted The p...

Page 145: ... BUFF or HOLD was used to obtain the bus During an inquire cycle that hits a modified cache line the processor asserts ADS as soon as two clocks after asserting HITlVI regardless of whether AHOLD is asserted or negated By contrast if BUFF or HLDA is asserted instead of AHOLD during an inquire hit the processor postpones the writeback until after BUFF or HLDA is negated During special bus cycles an...

Page 146: ...serting EA1JS with the inquire address and the processor is driving a Branch Trace Message special bus cycle at the same time that AHOLD or BUFF is asserted the branch address information driven by the proces sor on A31 A3 can be overwritten by the inquiring bus master In such cases system logic should latch A31 A3 when ADS is asserted before asserting AHOLD or BUFF At the falling edge of RESET th...

Page 147: ... In systems that would other wise place large capacitive loads on ADS the AlJS C output can be used instead of ADS to distribute loads thereby increasing response time Driven andFloated AD5C is driven and floated with the same timing as ADS See the description of ADS on page 5 25 Details See the description of ADS on page 5 25 5 28 Bus Interface ...

Page 148: ...ree methods by which system logic can obtain control of the address bus to drive an inquire cycle AHOLD BUFF or HOLD AHOLD obtains control only of the address bus and allows another master or system logic to drive only inquire cycles whereas BUFF and HOLD obtain control of the full bus address and data allowing another master to drive not only inquire cycles but also read and write cycles AHOLD an...

Page 149: ...hroughout an inquire cycle and any required writeback system logic must latch the inquire cycle address when it asserts EA1JS This is required so that if the inquire cycle hits a modified line HITlVI asserted the address used for the writeback need not be driven by the processor when the processor asserts ADS for the writeback Instead A31 A5 remains an input only bus and system logic must use its ...

Page 150: ...r the address bus so as to avoid deadlock contention for the bus Ground bounce spikes can be avoided by following two rules with respect to AHOLD Do not negate AHOLD in the same clock that BRDY is asserted during a write cycle Do not negate AHOLD in the same clock that ADS is asserted during a writeback These restrictions must be observed because the processor s 32 address drivers turn on almost i...

Page 151: ... bits is even on AP and A31 A5 the address is con sidered free of error thus the term even parity If the total number of 1 bits is odd he address is considered to have an error The bit values driven on A4 A3 are not counted during the parity checking In addition to generating and checking address parity the pro cessor also generates and checks data parity using the DP7 DPO and PCHK signals See pag...

Page 152: ...ock two clocks after system logic asserts EADS with an inquire address APCHK is driven under the same conditions in which EADS is sampled See the description of EADS on page 5 59 System logic can use APCHK to initiate a remedy for the error Typical PC systems assert an interrupt such as NMI if a parity error is detected See the description of parity error determination for the AP input on page 5 3...

Page 153: ...mplete a bus cycle that had been initiated before AHOLD was asserted or for inquire cycle writebacks During the Shutdown Halt and Stop Grant states BE7 BEU is driven only for inquire cycle writebacks BE7 BEU is not driven during the Stop Clock state or while BUFF HLDA RESET or INIT is asserted Table 5 5 shows the relationship between BE7 BEU D63 DO DP7 DPO and the effective relationship with A2 AO...

Page 154: ... which of the eight bytes on D63 DO are valid During writebacks 32 byte four transfer bursts with CACHE asserted the processor drives all bits of BE7 BEU Low to indicate that all eight bytes on D63 DO are valid Write backs are addressed by A3i A3 but they are always aligned to 32 byte boundaries so A4 A3 are always O TABLE 5 5 Relation Of BE7 BEO To Other Signals Byte Enable Effective Address Bits...

Page 155: ...E7 BEU A31 A3 Special Bus Cyelet Cause Notes I 2 5 J6 FEh 00h Shutdown Triple fault FDh 00h Cache Invalidation INVD instruction FBh 10h Stop Grant STPCLK FBh 00h Halt HLT instruction F7h 00h Cache Writeback and WBINVD instruction Invalidation EFh 00h FLUSH Acknowledge FLUSH Bit 5 1 and bits 3 1 001 in DFh 00h Branch Trace Message2 the Hardware Configuration Register HWCR See Section 7 1 on page 7 ...

Page 156: ...ternal pullup resistor see the data sheet for details Table 5 7 shows the ratios between the processor clock and the bus clock CLK for the High and Low values of BF BF may be tied High or Low Due to the internal pullup resistor the lower ratio is selected if BF is left unconnected TABLE 5 7 Processor to Bus Clock Ratios State of BF Input Processor Clock to Bus Clock Ratio BF 1 L5x BF O 2 0x Notes ...

Page 157: ...r Stop Grant states or while AHOLD RESET INIT or PRDY is asserted BUFF is sampled but not effective when HLDA is asserted BUFF is not sampled during the Stop Clock state The assertion of BUFF like HOLD but unlike AHOLD forces the processor to relinquish the full address and data bus to another bus master The signal can be used for the following purposes Bus Turnaround Another bus master can assert...

Page 158: ...es are floated Table 5 8 shows the signals floated The same set of signals is floated with HLDA TABLE 5 8 Outputs Roated When BUFF is Asserted Address and Cycle Data and Cache Address Parity Definition Data Parity Control and Control A31 A3 D C D63 DO CACHE ADS IDCK DP7 DPO PCD ADSC MIIU N A PWT AP SCYC N A N A BE7 BEU W R N A N A The processor supports only one in progress bus cycle no pending bu...

Page 159: ...ed before their last BRDY and the cycles not yet run are restarted after BUFF is negated Thus system logic must keep track of all cycles in the locked operation that have completed before the assertion of BUFF and must continue the locked operation immediately after BUFF is negated except that if a writeback is pending when BUFF is negated the writeback takes precedence over the restarting of the ...

Page 160: ...riptions AMD AMD5 6 Processor Technical Reference Manual If BUFF is asserted when BusCHK is asserted BUFF is recog nized and BUSCHK is ignored For a list of signals recognized while BUFF is asserted see Table 5 2 on page 5 9 5 41 ...

Page 161: ...een initiated before AHOLD was asserted or for inquire cycle writebacks During the Shutdown Halt and Stop Grant states BRDY is sampled only for inquire cycle writebacks BRDY is not sampled when the processor is not driving an external bus cycle or during the Stop Clock state or while BOFF HLDA RESET or INIT is asserted If BRDY is asserted simultaneously with BOFF BOFF is recog nized and BRDY is no...

Page 162: ...our transfers of the burst All data transfers that are not performed as bursts are per formed as one or more single transfer cycles For write cycles EWBE must be asserted either with or after BRDY in order for any further writes or certain other operations to be performed see the description of EWBE on page 5 63 If system logic returns more BRDYs than the processor expects for a single transfer cy...

Page 163: ...ition to the above uses of BRDY on the 486 processor BRDY on the AMD5K 86 and Pentium processors is used for both single transfer and burst cycles and it terminates special bus cycles Unlike BRDY on the 486 processor BRDY on the AMD5K 86 and Pentium processors is used for both single transfer and burst cycles and it terminates special bus cycles On the 486 processor single transfer cycles and spec...

Page 164: ...creasing response times BRDYC is sampled with the same timing as BRDY See the description of BRDY on page 5 42 See the description of BRDY on page 5 42 Unlike BRDY BRDYC has an internal pullup resistor At the falling edge of RESET the states of BRDYC and BUs CHK control the drive strength on the A21 A3 not including A31 A22 ADS HI T M and WIR signals The drive strength is weak for all states of BR...

Page 165: ...t acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM or while AHOLD BUFF HLDA or PRDY is asserted BREQ is not driven in the Shutdown Halt Stop Grant or Stop Clock states or while RESET or INIT is asserted The processor observes a bus parking protocol It continues to drive the bus without an arbitration sequence in the absence of AHOLD BUFF or HOLD Syste...

Page 166: ...cles including cache writethroughs and writebacks 110 cycles locked cycles spe cial bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM or in the Shutdown Halt or Stop Grant states While AHOLD is asserted the processor samples BOSCHK only to complete a bus cycle that had been initiated before AHOLD was asserted or during writebac...

Page 167: ...ons remaining in the pipeline saves its state and gener ates a machine check exception 12h If the MCE bit is cleared to 0 the processor continues exe cution with the next instruction After asserting BUSCHK system logic must nevertheless return all BRDYs that the processor expects for the type of bus cycle that experienced the error one BRDY for single transfer cycles four BRDYs for burst cycles If...

Page 168: ... BOSCHK is asserted and recognizes latched interrupts in prior ity order when BUSCHK is negated The MCE bit in CR4 which enables machine check exceptions during BUSCHK also enables machine check exceptions dur ing data parity errors that are indicated on PCHK while PEN is asserted 5 49 ...

Page 169: ... is asserted The processor floats CACHE one clock after system logic asserts BUFF and in the same clock that the processor asserts HLDA The processor asserts CACHE for certain types of unlocked memory reads as specified by the operating system and for all writebacks writes of lines cached in the M state The asser tion of CACHE indicates the processor s intent to drive the read or write cycle as a ...

Page 170: ...ile the processor asserts CACHE KEN is not a factor in determining the state of the PCD or CACHE signals The processor drives both PCD and CACHE before it knows the state of KEN For details see the descriptions of KEN and PCD on pages 5 90 and 5 100 The MESI state of a cache line is determined at the time of the line fill by the states of the CACHE KEN PWT and WBfWT signals Table 5 9 shows the rel...

Page 171: ...l 32 bytes no no yes yes yes no no no State After Read2 shared shared exclusive shared exclusive modified Notes Don t care ornot applicable I 2 5 52 The PCD bit is one determinant ofthe state ofrACRE Transition occurs afteranyline fill Lines in shared MESI state are saidto be in writethraugh state Those in exclusive or mod ified MESI states are said to be in writeback state On the 486 processor by...

Page 172: ...ced to its minimum when sys tem logic turns CLK off The processor enters its Stop Clock state when system logic asserts STpCLK thus entering the Stop Grant state and subsequently turns CLK off thus enter ing the Stop Clock state In the Stop Clock state the proces sor s phase lock loop and I O buffers are disabled except for the I O buffers on CLK and the TAP signals While the proces sor is in the ...

Page 173: ...ed or for inquire cycle writebacks During the Shut down Halt and Stop Grant states DIC is driven only for inquire cycle writebacks DIC is not driven during the Stop Clock state or while BUFF HLDA RESET or INIT is asserted The processor floats DIC one clock after system logic asserts BUFF and in the same clock that the processor asserts HLDA The processor drives DIC according to whether the access ...

Page 174: ...O Mar1996 Signal Descriptions AMD AMD5 6 Processor Technical Reference Manual During special bus cycles the processor drives DiC 0 M IO 0 and WIR 1 The cycles are then differentiated by BE7 BEU and A31 A3 5 55 ...

Page 175: ...hs and writebacks I O cycles locked cycles special bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM or while PRDY is asserted While AHOLD is asserted D63 DO is driven or sampled only to complete a bus cycle that had been initiated before AHOLD was asserted or for inquire cycle writebacks During the Shutdown Halt and Stop Grant...

Page 176: ...ers of a burst and return all eight bytes corre sponding to the eight byte address on A31 A3 Furthermore the memory subsystem must determine the successive addresses depending on the starting address that the proces sor drives on A31 A3 as described in Table 5 4 on page 5 22 During writebacks the processor drives all bits of BE7 BEU Low to indicate that all eight bytes on D63 DO are valid Write ba...

Page 177: ...ven for each byte on DP7 DPO are considered with the bit values driven for each byte on D63 DO For example if the total number of 1 bits for the byte on D63 D56 is even for DP7 and D63 D56 the address is considered free of error thus the term even parity If the number of 1 bits is odd the byte is considered to have an error During single transfer read cycles parity is only checked for enabled byte...

Page 178: ...own Halt or Stop Grant state or while INIT or PRDY is asserted EADS is not sampled in the Stop Clock state or while RESET is asserted If BUFF and EADS are both asserted in the same clock that AHOLD is negated EADS is not recognized If EADS is asserted on the same clock that HOLD is negated both the AMDSK86 and the Pentium processors recognize this as a valid inquire cycle and process it correctly ...

Page 179: ...sserts HLDA and simulta neously drive INV and a cache line address on A31 A5 The processor latches the address on A31 A5 when EAITS is asserted 3 Wait two clocks watching for HITM and or HIT to be asserted If neither HIT nor HITM are asserted at the end of two clocks or if only HIT is asserted the inquire cycle termi nates EAITS can be asserted again in the same clock that HITM is negated If HITM ...

Page 180: ...not recognize this as a valid inquire cycle Inquire cycles can be implemented for every memory access by another caching master To do this system logic can generate EAlJS to the processor using the equivalent of AIJS from the other caching master An inquire cycle can hit a line that is in the process of being written back for a reason other than the inquire such as when the writeback is being done...

Page 181: ... clock including while the processor drives the address bus It can thus support inquire cycles every clock The AMD5K 86 and Pentium processors by comparison can sample EADS every other clock and the maximum inquire or invalida tion rate with inquire cycles is one every two clocks because HIT and HITlVI change state two clocks after EADS and EADS can be asserted in the same clock in which HITlVI is...

Page 182: ...ould assert EWBE when all external write buffers are empty thus indicating that the write to memory or liD has completed and that writes to the cache can take place Most systems tie EWER Low asserted thus allowing the speed of writes to be controlled only by BRDY If EWER is sampled negated with the BRDY of an external write cycle the processor does not do any of the following Write store buffer en...

Page 183: ...erted If system logic implements memory mapped 110 as non cache able memory the standard method EWBE on the AMD5K86 processor has the same effect on writes to memory mapped 110 as does EWBE on the Pentium processor neither processor reorders reads ahead of writes For more details on the function of EWBE see the following sections BRDY Page 5 42 HITlVI Page 5 74 BMJ Page 5 117 SMIACT Page 5 122 STP...

Page 184: ...If software has set the numeric error NE bit in CRO to 1 the processor reports unmasked floating point exception condi tions in the way specified for 287 and 387 coprocessors the processor asserts FERR to report the error externally while internally the processor generates a numeric error exception 10h while executing the next WAIT instruction or at the beginning of the next computational floating...

Page 185: ...ut is asserted FERR is negated and the pro cessor does not report unmasked floating point exception conditions externally DOS and Windows based pes typically clear the NE bit to o Only higher end operating systems such as the Windows NTTM operating system set the NE bit to 1 Bus Interface ...

Page 186: ...es Real Protected and Virtual 8086 and in SMM or in the Shutdown Halt or Stop Grant states or while AHOLD BUFF HLDA or RESET is asserted PLUSH is not sampled in the Stop Clock state or while INIT or PRDY is asserted If asserted at the falling edge of RESET FLUSH invokes the processor s three state float test System logic can drive the signal either synchronously or asynchronously see the data shee...

Page 187: ...es in the data cache are written back to memory If writebacks are not required the INVD instruction or RESET can be used to invalidate all contents of the caches When FLUSH is recognized at an instruction boundary the processor performs the following actions in the order shown 1 Flush Pipeline The processor invalidates all instructions remaining in the pipeline 2 Writeback and Invalidate The proce...

Page 188: ...rted during the Stop Grant state the signal is held pending until after the processor exits the Stop Grant state at which point it is acted upon No other interrupt or exception will intervene in a flush opera tion because such interrupts are not recognized until after the FLUSH Acknowledge special bus cycle which occurs at the end of all writebacks and invalidations The processor latches the asser...

Page 189: ...ols instruction fetching and the checker mimics its behav ior by sampling the fetched instructions as they appear on the bus Both processors execute the instructions in lock step The checker compares the state of the master s output and bidirec tional signals with the state that the checker itself would have driven for the same instruction stream Errors detected by the checker are reported on the ...

Page 190: ...ignals are tied together so that they run the same pro gram_ The Functional Redundancy Checking mode can only be exited by the assertion of RESET Functional redundancy checking cannot be done in the Hardware Debug Tool HDT mode The assertion of FRCMC is not recognized while PRDY is asserted 5 71 ...

Page 191: ...d INV Inquire cycle logic in systems with look aside caches can be simplified by monitoring only IIITM and ignoring HIT This works because the resulting state of a hit line is determined only by the state of the INV input during the assertion of EADS If INV is negated during a hit the hit line whether shared exclusive or modified transitions to the shared state Thus the inquiring master can safely...

Page 192: ...l The write once protocol requires caching in the exclusive state at certain transitions and the exclusive state can only be identi fied if both HIT and HITM are monitored For details on this protocol see Section 6 2 6 on page 6 19 Inquire cycles can be driven while LUCK is asserted if AHOLD is used to obtain the bus for the inquire cycle An inquire cycle cannot hit a line that is involved in a lo...

Page 193: ...lock state or while RESET or INIT is asserted The processor asserts IIITM when an inquire cycle address matches the address of a modified line in the processor s data cache The processor then attempts to drive a four transfer burst writeback of the modified line If INV was asserted at the time EAUS was asserted for the inquire cycle a hit leaves the written back line in the invalid state If INV wa...

Page 194: ...cycle An inquire cycle cannot hit a line involved in a locked operation Cached locations that are about to be accessed in locked opera tions are written back and invalidated before the locked opera tion occurs If such an inquire cycle hits a modified location that is different than the one involved in the locked operation the writeback is done in the middle of the locked operation between the two ...

Page 195: ...ter HOLD is negated HLDA is driven during cache hits in the normal operating modes Real Protected and Virtual 8086 and in SMM but writebacks wait until HLDA is negated HLDA is also driven in the Shutdown Halt Stop Grant and Stop Clock states or while AHOLD BUFF RESET INIT or PRDY is asserted HLDA is not driven during processor originated bus cycles because any such pending bus cycle completes befo...

Page 196: ...g HOLD with HLDA System logic may assert EADS for an inquire cycle as early as one clock after the processor asserts HLDA The processor continues driving HLDA until two clocks after HOLD is negated at which time the processor may again drive its own cycles with ADS in the next clock after it negates HLDA The processor responds to inquire cycles while HLDA is asserted and will assert HIT and IIITM ...

Page 197: ...Stop Clock states or while AHOLD BUFF RESET INIT or PRDY is asserted HOLD is not sampled dur ing locked cycles or interrupt acknowledge operations The assertion of HOLD like BUFF but unlike AHOLD forces the processor to relinquish the full address and data bus to another bus master The signal can be used for the following purposes Bus Turnaround Another bus master can assert HOLD to the processor ...

Page 198: ... its own cycles with ADS in the next clock after it negates HLDA During the time HOLD is asserted the pro cessor attempts to operate out of its cache If it can no longer do so it asserts BREQ continuously There are three methods by which system logic can obtain con trol of the address bus to drive an inquire cycle AHOLD BDFF or HOLD AHOLD obtains control only of the address bus and allows another ...

Page 199: ... the checker if FRCMC is asserted at RESET In this mode all of the processor s output and bidirectional signals except IERR and TDO are floated and tied to those of the master pro cessor Both processors execute the same instructions and the checker compares the state of the master s output and bidirec tional signals with the state that the checker itself would have driven for the same instruction ...

Page 200: ...s are designed for backward com patibility with floating point software designed for 286 and 386 IBM compatible PC AT systems running DOS If software has cleared the numeric error NE bit in CRO to 0 unmasked floating point exception reporting depends on the state of the IGNNE input as follows If the IGNNE input is negated the processor reports unmasked floating point exception conditions in a way ...

Page 201: ... states or while AHOLD BOFF HLDA or RESET is asserted INIT is not sampled in the Stop Clock state or while PRDY is asserted If INIT is asserted on the falling edge of RESET the processor performs its built in self test BIST before initialization and code fetching begin System logic can drive the signal either synchronously or asynchronously see the data sheet for syn chronously driven setup and ho...

Page 202: ...uffer TLB 2 Reinitialize The processor reinitializes the following resources to reset values General purpose registers System registers 3 Jump To BIOS The processor jumps to the BIOS at address FFFF_FFFOh the same entry point used after RESET See the description of RESET on page 5 110 for details on the aliasing of this boot address Unlike RESET INIT does not reinitialize the data and instruc tion...

Page 203: ... boot process after the BIST completes whether the BIST passed or failed The processor recognizes BUFF HOLD AHOLD and RIS while INIT is asserted but these signals will not intervene in the ini tialization process except that they will prevent the first code fetch jump to BIOS after the registers are initialized No other exceptions or interrupts will intervene in the initial ization process The fir...

Page 204: ...rating modes Real Protected and Virtual 8086 and in SMM or in the Halt state INTR is not sampled in the Shutdown Stop Grant or Stop Clock states or while AHOLD BOFF or HLDA RESET INIT or PRDY is asserted INTR is the seventh highest priority external interrupt For details on its relationship to other interrupts and exceptions see Section 5 1 3 on page 5 14 and Table 5 3 on page 5 17 System logic ca...

Page 205: ...provided only for compatibility with the original protocol it carries no useful information TABLE 5 13 Interrupt Acknowledge Operation Definition Processor First Bus Cycle Second Bus Cycle Outputs D C 0 0 MIID 0 0 W R 0 0 BE7 BEU EFh FEh low byte enabled A31 A3 0 0 D63 DO ignored Interrupt vector expected from interrupt controller on D7 DO 3 Disable Interrupts The processor clears the IF bit in th...

Page 206: ... has been entered for example the access to the IDT address The processor disables INTR interrupts during all software interrupts by clearing the IF bit in EFLAGS Software may re enable INTR interrupts by setting IF to 1 again on entering the service routine In this context software interrupts include In Real mode any INTn instruction In Protected mode any INTn instruction that vectors to an IDT e...

Page 207: ... interrupts can intervene in the INTR interrupt on entry into the INTR service routine INTR is not recognized if asserted while AHOLD BUFF or HLDA is asserted because the processor cannot drive the interrupt acknowledge operation and therefore cannot obtain the interrupt vector Bus Interface ...

Page 208: ... is typically asserted during a write by another caching master In such cases INV can be generated by watching W R from another bus master and asserting INV to the processor along with EADS only on writes This method invalidates a copy that the processor may have cached whether modified or not for the same location being written by the other bus mas ter The processor s assertion of III1 M and or H...

Page 209: ...pled only to complete a bus cycle already begun before the asser tion of AHOLD System logic typically maintains a specification of address cacheability in external registers that are written by BIOS at boot time The BIOS does this by knowing or determining the address ranges of memory mapped I O ports and other loca tions that should be noncacheable For example video and net work boards are normal...

Page 210: ... the cache ways in which a potential line fill can be cached are already filled with valid entries the processor selects a line to replace during the line fill In the data cache if the selected line is in the modified state the processor writes the modified line back to memory before filling the vacated cache line with the new contents If BUFF is asserted after the first eight bytes BRDY and KEN o...

Page 211: ...r PRDY is asserted While AHOLD is asserted LOCK is driven only to complete a locked cycle that had been initiated before AHOLD was asserted The processor floats mcK one clock after system logic asserts BOFF and in the same clock that the processor asserts HLDA The processor always locks the following types of memory operations Interrupt Acknowledge Operations These are a pair of read cycles used t...

Page 212: ...he processor sets them so that the operating system can thereafter identify pages that have been accessed and updated XCHG Instruction When XCHG is used to swap a register with a memory location the access is unconditionally locked LOCK Prefix Applications programs can add the LOCK prefix to the following instructions if the destination oper and resides in memory ADC ADD AND BT BTC BTR BTS DEC INC...

Page 213: ...uring the writeback System logic must recognize this case and know that the inquire cycle is snooping and writing back a different location than the one that is locked Locked operations cannot be performed on cached locations and an inquire cycle cannot hit a line that is involved in the locked operation The processor prevents this by always check ing its cache tags prior to a locked operation If ...

Page 214: ... and exceptions are not recognized during locked operations The processor samples BUSCHK if it is asserted with any BRDY of a locked operation but the processor does not generate an enabled machine check interrupt for the BOSCHK until after the locked operation completes and thus the exception will not intervene in the locked operation If an edge triggered inter rupt FLOSR sm INIT or NMI is assert...

Page 215: ... 96 The processor accesses I O when it executes an I O instruction any of the INx or OUTx instructions The processor accesses memory when it fetches instructions or executes an instruction that loads or stores data Accesses to memory mapped I O ports appear on the bus as memory accesses Only data not code can be read or written from the I O address space the cycle definition for an I O code read D...

Page 216: ...ns or in the Shutdown Halt Stop Grant or Stop Clock states or while BUFF HLDA RESET INIT or PRDYis asserted While AHOLD is asserted NA is sampled only to complete a bus cycle already begun before the assertion of AHOLD NA is an input that is asserted when external memory is pre pared to accept a pipelined cycle The AMD5K 8G processor drives the pending ADS two clocks after NA is sampled active NA ...

Page 217: ...rocessor rec ognizes the INIT after leaving the Stop Grant state then it rec ognizes the NMI prior to fetching any instructions Current implementations of the Pentium processor do not recognize the NMI in such cases although future implementations may NMI is the sixth highest priority external interrupt For details on its relationship to other interrupts and exceptions see Sec tion 5 1 3 on page 5...

Page 218: ...er vice routine The processor recognizes BUFF HOLD and AHOLD while NMI is asserted and these signals will intervene in the NMI ser vice routine The processor latches the assertion of any edge triggered interrupt FLUSH sm INIT NMI while BUSCHK is asserted and recognizes latched interrupts in priority order when BUSCHK is negated If NMI is asserted during the Stop Grant state the signal is held pend...

Page 219: ...LDA RESET INIT or PRDY is asserted The processor floats PCD one clock after system logic asserts BUFF and in the same clock that the processor asserts HLDA If PCD is negated during read misses the page being accessed mayor may not be cacheable depending on the state of other signals If PCD is asserted during any type of access the page is noncacheable The PCD output affects the processor s cach in...

Page 220: ...n page 5 106 The cache disable CD and not writethrough NW bits in CRO are cleared to 0 for normal cacheable operation If a location is already cached before the operating system sets a PCD bit to 1 any access to that location will hit in the cache regardless of the state of the PCD bit or signal CACHE is partially determined by the PCD bit Thus the states of CACHE and PCD are very often the same C...

Page 221: ...riven on D63 DO If the total number of 1 bits is even for DP7 DPO and D63 DO the byte is considered free of error thus the term even parity If the num ber of 1 bits is odd the byte is considered to have an error During burst reads the processor checks all eight bytes of D63 DO for errors with respect to the even parity bit sampled on DP7 DPO During single transfer reads only the enable bytes on D6...

Page 222: ...AHOLD If PEN is asserted when a data parity error is reported on PCHK the processor latches the physical address and cycle definition of the failed bus cycle in its 64 bit machine check address register MCAR and its 64 bit machine check type register MCTR These registers can be read with the RDMSR instruction See Section 3 3 5 on page 3 35 for details on this instruction In addition to latching th...

Page 223: ...esses and lID cycles in the normal oper ating modes Real Protected and Virtual 8086 and in SMM in the Shutdown Halt or Stop Grant states or while AHOLD BUFF HLDA or RESET is asserted PRDY is not driven dur ing locked cycles special bus cycles or interrupt acknowledge operations during the Stop Clock state or while INIT is asserted The HDT is entered either when external debug logic drives RfS Low ...

Page 224: ...AMD AMD5J 16 Processor Technical Reference Manual Documentation on the HDT is available under nondisclosure agreement to test and debug developers For information con tact your AMD sales representative or field application engi neer 5 105 ...

Page 225: ... in the Shutdown Halt or Stop Grant states except for writebacks due to inquire cycles and PWT is never driven during the Stop Clock state or while BUFF HLDA RESET or INIT is asserted The processor floats PWT one clock after system logic asserts BUFF and in the same clock that the processor asserts HLDA As Table 5 14 shows lines in the modified or exclusive MESI state are said to be in the writeba...

Page 226: ...ritethrough PWT bit in one of three locations The selection of bits depends on the pro cessor s operating mode and the type of access as follows In Real mode and in Protected and Virtual 8086 modes while paging is disabled PG bit in CRO cleared to 0 PWT output Low writeback In Protected and Virtual 8086 modes while paging is enabled PG bit in CRO set to 1 For accesses to I O space page directory e...

Page 227: ...down Halt or Stop Grant states or while AHOLD BUFF HLDA RESET or INIT is asserted R S is not sampled during locked cycles special bus cycles or interrupt acknowledge operations or during the Stop Clock state R S is the second highest priority external interrupt For details on its relationship to other interrupts and exceptions see Section 5 1 3 on page 5 14 and Table 5 3 on page 5 17 Test logic ca...

Page 228: ...et The processor recognizes AHOLD BOFF and HOLD while RiS is Low and these signals will intervene in the HDT mode when PRDY is asserted However exceptions or interrupts are not recognized in the HDT mode The processor latches the asser tion of any edge triggered interrupt FLUSH sm INIT NMI during the HDT mode and recognizes them in priority order when PRDY is negated See Table 5 3 on page 5 17 for...

Page 229: ... initialization and code fetching begin The processor samples RESET at all times except in the Stop Clock state and while INIT or PRDY is asserted System logic can drive the signal either synchronously or asynchronously see the data sheet for synchronously driven setup and hold times RESET is typically asserted at power up by a power good sig nal from the power supply which is turned on by a hardw...

Page 230: ...upt flag IF in EFLAGS to 0 3 Jump To BIOS The processor jumps to physical address FFFF_FFFOh the same entry point used after INIT where it expects to find the BIOS entry point The contents of AMD5K86 processor registers at the conclusion of RESET or INIT is identical to that of the Pentium processor except that the CPU ill in EDX is OOOO_050xh The upper byte of DX DH contains 05h and the lower byt...

Page 231: ... 0000_0000 FPU Stack R RO 0000_0000_0000_0000_0000 FPU Exception Pointer 0_0000_0000_0000 CS FOOO SS 0000 DS 0000 ES 0000 FS 0000 GS 0000 GDTR base OOOO_OOOO limit OOOO IDTR base OOOO_OOOO limit OOOO TR 0000 LDTR 0000 CRO 6000_0010 CR2 0000_0000 CR3 0000_0000 CR4 0000_0000 DR 0000_0400 DR6 FFFF_OFFO DR3 0000_0000 DR2 0000_0000 DRl 0000_0000 DRO 0000_0000 5 112 Bus Interface ...

Page 232: ... RESET differs by reinitializing the contents of the caches floating point registers control registers and model specific registers as well as all other states that are reinitialized by INIT AZOM should not be asserted during RESET The operating system alone is responsible for controlling the state of AZOM by writing to an external register provided for this purpose See the description of AZOM on ...

Page 233: ...ion only begins to work in the normal Real mode manner when the first far jump is executed This jump loads the code segment register with a 16 bit segment selector This code segment load causes the address translation mecha nism to begin working normally The system logic address decoder must make this behavior transparent to software by aliasing the physical address FFFF_FFFOh to the physical addr...

Page 234: ...mplete a locked memory cycle already begun before the assertion of AHOLD The processor floats SCYC one clock after system logic asserts BUFF and in the same clock that the processor asserts HLDA For purposes of bus cycles the term aligned means 2 and 4 byte transfers lie within 4 byte address boundaries 8 byte transfers lie within 8 byte address boundaries For purposes of exceptions the term align...

Page 235: ...AMDSK86 processor runs the bus cycles in the opposite order of the Pentium processor The AMDSK86 processor trans fers the low address portion followed by the high address por tion instead of the high address portion followed by the low address portion I O writes however are performed in the same order on both processors Bus Interface ...

Page 236: ... to be recognized on the instruction boundary associated with that BRDY sm is sampled during memory cycles including cache writethroughs and writebacks cache accesses 110 cycles locked cycles special bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM in the Shutdown Halt or Stop Grant states or while AHOLD BUFF or HLDA is assert...

Page 237: ...erted the proces sor asserts sMIACT to acknowledge the interrupt At that point system logic must ensure that all memory accesses during SMM are to the SMM memory space 4 Save Processor State The processor saves its state in a 512 byte SMM state save area at the top of the 32 Kbyte SMM memory area starting at default physical location 0003_FFFFh and filling down 5 Disable Interrupts and Debug Traps...

Page 238: ...y are simpler and may perform better However if SMM memory space overlaps main memory space that is cacheable PLUSH must be asserted when SID is asserted so that memory accesses in SMM do not hit locations cached from main memory The FLUsH is per formed first because it is a higher priority interrupt If SMM memory is to be cacheable FLOSH should also be asserted with SID when entering SMM and the ...

Page 239: ...ebug breakpoint trap the AMD5K 86 processor responds to the sm first and postpones writing the exception related information to the stack until after the return from SMM via the RSM instruction If debug registers DR3 DRO are used in SMM they must be saved and restored by the SMM software the processor automatically saves and restores DR7 DR6 If the I O trap restart slot in the SMM state save area ...

Page 240: ...upt before executing the first instruction of the INTR handler By contrast the AMDSK 86 processor recog nizes a pending NMI interrupt after returning via the IRET instruction from a prior interrupt The same dummy interrupt used on the Pentium processor to enable NMI recognition during SMM works on the AMDSK 86 processor The only difference is that the AMDSK 86 processor responds to the NMI after t...

Page 241: ...IACT is driven during memory cycles including cache writethroughs and writebacks cache accesses I O cycles locked cycles special bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM in the Shutdown Halt or Stop Grant states or while AHOLD BUFF HLDA or PRDY is asserted SMIACT is not driven in the Stop Clock state or while RESET is ...

Page 242: ...10 cycles locked cycles special bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM or in the Shutdown Halt or Stop Grant states STPCLK is not sampled in the Stop Clock state or while RESET INIT or PRDY is asserted STPCLK is not meaningful if it is asserted while AHOLD BUFF or HLDA is asserted because the processor cannot drive t...

Page 243: ...ed the pro cessor drives a Stop Grant special bus cycle This cycle is identified by D C 0 MIID 0 WIR 1 BE7 BEU FBh and A31 A3 10h System logic must respond with BRDY 4 Stop Internal Clock When system logic returns BRDY for the Stop Grant special bus cycle the processor stops its internal clock and floats D63 DO and DP7 DPO 5 Optional Stop Bus Clock After returning BRDY in response to the Stop Gran...

Page 244: ...turns the processor to the Halt state Otherwise negation of STPcLK or assertion of RESET returns the processor to a normal operating mode Real Protected or Virtual 8086 or SMM If INIT is asserted in the Stop Grant state the signal is latched and acted upon after STPCLK is negated No processor registers are saved before entering the Stop Grant state because the processor returns to the next unexecu...

Page 245: ...phase lock loop is synchronized The latter takes several clocks see the data sheet for this specification The CLK can be driven with a different frequency and or the bus to processor clock ratio can be changed on the BF input upon restarting CLK Thus when CLK is restarted the processor can Respond to AHOLD BUFF or HOLD in the next clock after CLK restarts and Transition to the Stop Grant Inquire s...

Page 246: ...TPCLK is negated The AMD5K 86 and Pentium processors differ in their support for STPCLK in the following ways In the Halt state the AMD5K 86 processor responds to STF eLK by entering the Stop Grant state The Pentium proces sor ignores StPCLK in the Halt state The Pentium processor guarantees that at least one instruc tion will be executed between the negation of STPcLK and a subsequent reassertion...

Page 247: ... uts on TDO are driven valid on the falling edge of TCK When TCK stops on its falling edge the state of test latches in the processor are held Section 7 8 on page 7 19 summarizes the implementation of TAP testing on the AMDSK 86 processor System logic should tie TCK High if TAP testing is not implemented See the IEEE Standard Test Access Port and Boundary Scan Architecture IEEE 1149 1 specificatio...

Page 248: ... but only during the shiftJR and shifcDR states TDI has an internal pullup resistor TDI is always sampled except while RESET or INIT is asserted Instructions are shifted into the processor on TDI during the shiftJR TAP state Data are shifted into the processor on TDI during the shifcDR TAP state See the IEEE Standard Test Access Port and Boundary Scan Architecture IEEE 1149 1 specification for a d...

Page 249: ...DR states It is floated at all other times Details 5 130 TDO is always driven except when floated and while RESET or INIT is asserted Instructions are shifted out of the processor on TDO during the shiftjR TAP state Data are shifted out of the processor on TDO during the shifcDR TAP state See the IEEE Standard Test Access Port and Boundary Scan Architecture IEEE 1149 1 specification for a descript...

Page 250: ...ing TCK edge TMS has an internal pullup resistor TMS is always sampled except while RESET or INIT is asserted If TMS is asserted for five or more clocks the TAP controller enters its test reset Iogic state regardless of the controller state This action is the same as that achieved by asserting TRST See the IEEE Standard Test Access Port and Boundary Scan Architecture IEEE 1149 1 specification for ...

Page 251: ...r TRST is always sampled except while RESET or INIT is asserted When TRST is asserted the TAP controller enters its test reset logic state regardless of the controller state This action is the same as that achieved by holding TMS asserted for five or more clocks The assertion of TRST is unnecessary at RESET because the processor performs the TAP reset auto matically at that point See the IEEE Stan...

Page 252: ... the processor fetches an instruction or reads or writes a data operand it checks the associated code or data segment descriptor to verify that such action is permitted The execute E bit in the segment descriptor maintained by the operating system distinguishes between data and code segments and the R W bit specifies the segment s read and write properties Code segments can only be read data and s...

Page 253: ...data cache or hits a shared line in the data cache the processor drives a 1 to 8 byte write cycle called a writethrough on the bus When an inquire cycle internal snoop FLUSH operation or WBINVD instruction hits a modi fied line in the data cache the processor drives a 32 byte burst write cycle called a writeback on the bus Table 2 2 on page 2 19 shows the relationships between cache accesses write...

Page 254: ...or Reads Result of Cache Lookup Signal or Event Read Hit Read Miss shared exclusive modified CACHE PCD 1 0 0 0 KEN 1 0 0 0 PWT 1 0 WBIWT 0 1 Cache Line Fill 32 bytes no no yes yes yes no no no State After Read2 shared shared exclusive shared exclusive modified Notes Don t care ornot applicable 1 The PCD bitis one determinant ofthe state ofrACRE 2 Transition occurs after anyline fill Lines in share...

Page 255: ...I WT is typically tied High This allows the processor to cache all cacheable reads in the exclusive state and all cacheable writes update only the cache In systems with multiple caching mas ters WBIWT can be generated after inquire cycles to all other caching masters by the logical OR of HIT from all of the mas ters This allows the processor to cache reads in the exclusive or modified state only i...

Page 256: ...tructions or data MIIO specifies whether the cycle accesses memory or an I O port W R specifies whether the cycle is a read or write The assertion of CACHE indicates that the processor is writing or is prepared to read a burst cycle consisting of four consecutive transfers on the data bus However for a read system logic must confirm the burst by asserting KEN or the bus cycle becomes a single tran...

Page 257: ...les are always aligned The last expected BRDY represents the completion of a proces sor initiated bus cycle The processor guarantees at least one idle clock between consecutive bus cycles whether unlocked or locked This means that consecutive locked operations which consist of consecutive bus cycles also have at least one idle clock between them Addressing The address for a bus cycle is driven on ...

Page 258: ... a second bus cycle which will nor mally occur immediately after the first bus cycle unless inter vened by an interrupt or bus backoff If the misaligned transfer is run as a locked cycle the processor asserts both LOCK and SCYC throughout the misaligned sequence of bus cycles If memory reads memory writes or I O reads are misaligned the AMDSK 86 processor runs the bus cycles in the opposite order ...

Page 259: ...4 for a DRAM page miss On a 50 MHz bus there is no change in timing for EDO DRAM but Page mode DRAM timing becomes 6 3 3 3 for a DRAM page hit and 8 3 3 3 for a DRAM page miss Bus Cycle Priorities The AMD5K 86 processor can support only one on going bus cycle at a time pending bus cycles are not buffered System logic maintains the ultimate control over the bus The proces sor asserts BREQ to reques...

Page 260: ...CMC and INIT Sampled on the falling edge of RESET TDI TDO TMS and TRST Sampled relative TCK For each signal in the timing diagrams the High level repre sents 1 the Low level represents 0 and the middle level repre sents the floating high impedance state When both the High and Low levels are shown the meaning depends on the signal For a single signal it means don t care For a bus it means that the ...

Page 261: ...supporting very fast memory devices During the read cycle the processor drives PCD PWT and CACHE to indicate its caching and cache coherency intent for the access System logic returns KEN and WBIWT to either con firm or change this intent In this example the processor asserts PCD and negates CACHE so the accesses are non cacheable even though system logic asserts KEN during the BRDYs to indicate i...

Page 262: ...n its 64 bit machine check address register MCAR and its 64 bit machine check type register MCTR For details on such parity errors see the descriptions of PCHK and PEN on pages 5 102 and 5 103 While Figure 5 2 shows BRDY returned in the next clock after ADS most DRAM based systems add wait states idle clocks between ADS and BRDY as described in Section 5 3 4 on page 5 140 5 14J ...

Page 263: ...nual 18524BjO Mar1996 ClK A31 A3 ADS I I AP I IlE7 Jmj X X X BlWY I I BREQ I lJ ffiE D C D63 DO I DP7 DPO m J I I MjID PCD JlO1R I PEN PWT W R I WB WT I I ClK I Read I Write I FIGURE 5 2 Single Transfer Memory Read and Write 5 144 Bus Interface ...

Page 264: ...t asserting BRDY is that negating EWER prevents only write requests but not asserting BRDY stalls the bus and prevents all requests More specifically if EWER is negated with or after the last BRDY of a write cycle the processor will not do any of the fol lowing Write a store buffer entry to the data cache Write to memory single transfer or burst including locked write to Accessed A bit after TLB l...

Page 265: ...3 c t x _ _________ ____ ___ _ L _i_ _r____ _ __ J K I ADS L Jr i l1r m7 mTI c JJr K K 1 BRU I D C J D63 DO EWBE M ID W R 1J ClK I I I I L J c J i r rlc b i I Write I Effective I BRDY I i I Write FIGURE 5 3 Single Transfer Memory Write Delayed by IWBE Signal 5 146 Bus Interface ...

Page 266: ...cycle protocol is nearly the same as the protocol for read and write accesses to memory shown in Figure 5 2 except that MIIO 0 Only data not code can be read or written from the I O address space The cycle definition for an I O code read D C 0 MIIO 0 W R 0 defines an interrupt acknowledge cycle and the cycle definition for an 110 code write D C 0 MIIO 0 W R 1 defines a special bus cycle The exampl...

Page 267: ...s SEh This transfer also crosses a doubleword bound ary so it is misaligned The processor writes the word to I O address 90h followed by the word to I O address SEh The AMD5K S6 processor performs misaligned memory read memory write and I O read transfers in the reverse order of the Pentium processor but misaligned I O write transfers are performed in the same order on both processors Table 5 20 s...

Page 268: ...Manual ClK Ml A3 __ ______ ____ A ______________A __ ______ __________ I i r r r BE 1lEO CJ X X IlROY oj J 063 00 MfID sevc W R elK I Read x I a ___ ___ I Read I Write I Write FIGURE 5 5 Single Transfer Misaligned Memory and I O Transfers Bus Cycle Timing 5 149 ...

Page 269: ...gure 5 6 shows two consecutive burst reads During burst reads CACHE and KEN both asserted with the first BRDY of a memory read the processor drives BE7 BEU with ADS to identify the bytes of the desired instruction or operand The processor drives BE7 BEU with the desired bytes at that time because it does not yet know whether the read will be a single transfer or a burst this depends on how system ...

Page 270: ...and system logic asserts KEN with the BRDY of the first trans fer Thus CACHE and KEN agree and the access is cached This agreement between CACHE and KEN is required in order for a burst read to occur The processor only drives burst reads if the access is cacheable If either CACHE or KEN were negated during the BRDY of the first transfer the read would terminate with the first quadword transfer thu...

Page 271: ...T are validated by either NA or BRUY whichever comes first NA will not gen erate a pipelined cycle in the event that there are no pending internal cycles I IVk nlk h 1 hi I I I I I qx I i i I 1 i I I I i LjJ I tl j I fbbb I i i i I I I i i nn r C X C X I I I vi ILl I I I I I I I I I I I I I I I i i i i I i i i I Ii I I i I I Read I Read FIGURE 5 6 Burst Reads 5 152 Bus Interface ...

Page 272: ...MD5 6 Processor Technical Reference Manual ClK A31 A3 I i Jr L JID BRl c x x i 0 BRDY r _ _ _ J _ ______ I rtl I 41 r LAmE DfC D63 DO NT W R WB M ClK I I Read FIGURE 5 7 Burst Read NJ Sampled Bus Cycle Timing I I I Read 5 153 ...

Page 273: ...s a data cache line in the modified state the line is written back to memory before being in validated WBINVD Instruction When the processor executes a WBINVD instruction it writes back all modified lines in the data cache and then invalidates all lines in both caches The action taken in response to the WBINVD in struction is essentially the same as the action taken in response to the FLUSH input ...

Page 274: ...ttempted burst read finds that all four cache ways for that address are filled with valid entries In this case the processor performs the following sequence 1 Copies the prior contents of the replacement line to its 32 byte writeback buffer described in Section 2 3 7 on page 2 23 This is not visible on the bus 2 Completes the burst read placing the incoming data into the cache line This is the fir...

Page 275: ...ical Reference Manual 18524B O Mar1996 ClK A31 A3 O C 063 00 Ei iD5 KEN M TO PWT W R WB ifJT ClK x x x x I I 1 x t h 1 i I r Jhl T I I I I Read I Write FIGURE 5 8 Burst Writeback Due To Cache Line Replacement 5 156 Bus Interface ...

Page 276: ...en BDFF and AHOLD Due to its slow response time HOLD is usually considered only when backward compatibility with prior generation sub systems requires it or when the integrity of in progress bus cycles is of paramount importance Support for BDFF is usu ally needed to resolve potential deadlock problems that arise as a result of inquire cycles and if BDFF is supported there is usually no reason to ...

Page 277: ...F or HLDA is negated The resulting state of a cache line that is hit by an inquire cycle depends on the state of the INV signal at the time of the inquire cycle see Table 5 11 on page 5 73 If INV is negated the line remains in or transitions to the shared state If INV is asserted the line is written back if modified and transitions to the invalid state Figure 5 9 shows a burst read during which sy...

Page 278: ...d AHOLD and BUFF can be asserted in con junction with each other without interfering with EADS recog nition as long as the sampling criteria for at least one of the signals AHOLD or BUFF is met i I AlJS AHOLD AP APCRR BEJ llEO rnmv BREQ O C 063 00 EADS HIT RITJiil INV M lD W R ClK X J I I I Read I X FIGURE 5 9 AHOLD Initiated Inquire Miss Bus Cycle Timing I K I i I I t I x t x I I J I I I I Inquir...

Page 279: ... assertion of HIT and the negation of IIITM two clocks after the assertion of EADS The processor invalidates the cache line because sys tem logic asserts INV with EADS The processor may drive a new bus cycle as early as one clock after system logic negates AHOLD I A31 CI I i r t _ _ t t_ E_ I __ ____ ____ r i____ 1_ AHOLD IlFl EEO X K I I I i I DjC D63 DO tAOS RlT RITN I i i __ i I INV M ID W R Cl...

Page 280: ...red writeback system logic must latch the inquire cycle address when it asserts EADS This is required so that if the inquire cycle hits a modified line the address used for the writeback need not be driven by the processor when the processor asserts ADS for the writeback Instead A31 A5 remains an input only bus and system logic must use its latched copy of the inquire cycle address By contrast if ...

Page 281: ...524B 0 Mar1996 Ml t y ill I I I AHOLD DfC D63 DO HIT INV M ID W R elK I I I I _ _ _ _ J I I II 1 1 i I I I I I I I I I __ _ _ _ Jt _ __ _ _ _ _ _ __ I I Read Inquire Writeback FIGURE 5 11 AHOLD Initiated Inquire Hit to Modified Line 5 162 Bus Interface ...

Page 282: ...g cycles as early as two clocks after BUFF is asserted System logic or another bus mas ter may continue asserting BUFF for as long as it wants The processor has no way of breaking the hold While the processor is backed off it continues to execute out of its instruction and data caches if possible If it can no longer operate out of its caches it holds BREQ asserted continuously As early as one cloc...

Page 283: ...D5t J6 Processor Technical Reference Manual ClK A31 A3 D63 DO M fO WjR ClK I I Read Aborted FIGURE 5 12 Basic DOFF Operation 5 164 I I Cycle by Another Master I I Restarted Read 1B524BjO Mar1996 Bus Interface ...

Page 284: ... modified cache line The writeback can not occur while BUFF is asserted however because the proces sor has floated its data and control outputs After BUFF is negated the processor writes back the modified cache line holding HI TM asserted until one clock after the last BRDY of the writeback Because INV was asserted with EAUS the cache line is invalidated after its writeback Then the pro cessor res...

Page 285: ...ocessor Technical Reference Manual elK A31 A3 BI7 llEO B1W i LAmE Lj 18524B O Mar1996 I t Irr T I ul D63 DO r Ur W Writeback FIGURE 5 13 BUFF Initiated Inquire Hit to Modified Line 5 166 Restarted Read Bus Interface ...

Page 286: ...initiates an inquire cycle by asserting EXITS and INV and driv ing an inquire address on A31 A5 The inquire cycle hits a shared or exclusive line HIT asserted and HITlVI negated two clocks after EXITS and the processor invalidates the cache line not visible on the bus System logic negates HOLD in the clock after EXITS and two clocks later one clock after HIT and HITlVI transition the processor neg...

Page 287: ...AMD AMD5t1J6 Processor Technical Reference Manual 18524BjO Mar1996 i T ji T I i T I I I I I I I t __ I Inquire FIGURE 5 14 HOLD Initiated Inquire Hit to Shared or Exclusive Line 5 168 Bus Interface ...

Page 288: ...em logic negates HOLD in the clock after EADS and two clocks later one clock after HIT and IIITNI transition the processor negates HLDA As early as one clock after negating HLDA the processor asserts ADS to drive the writeback after which the processor invalidates its copy of the line MI BEl BED L ACRE o C 063 00 HLDA HOLD INV M fO t I I i I f J I Read I I I I fIl I I I Inquire RGURE 5 15 HOLD Ini...

Page 289: ...edge operations which are also locked consist of a pair of read cycles with no operand modification between the cycles Locked operations generated by the LOCK instruction prefix cause r ocK to be asserted only during bus cycles initiated by that single instruction The processor guarantees at least one idle or dead clock between consecutive bus cycles whether unlocked or locked This means that cons...

Page 290: ... BFJ BEO BlIDY LAmE DfC D63 DO M fO W R elK j lvX T T iKJb i J I i I i II LV I I iLif iLi dx IX I d J jri r JJ Ui i I U I I cb I LJ I I I I 1 1 1 __ rt OJ I j 4tt iJ i 1 I i i I I iu I I I I I I I Write I Write Read Read FIGURE 5 16 Basic Locked Operation Bus Cycle Timing 5 171 ...

Page 291: ...processor also checks and if necessary sets the PTE Dirty D bit The general sequence both for PDE and PTE is as follows for accesses to a 4 Kbyte page The processor drives an unlocked read of the PDE or PTE to see if the relevant bit A or D is set If the bit is cleared 0 the processor then drives a locked read modify write four byte read followed by four byte write to set the bit The example in Fi...

Page 292: ... ClK A31 A3 I I AlJS l I J _ J L J iL J I BIJ lffij D J X r r c r J x r I BRDY I LAmE J1 I O C J1 I 063 00 MjlD W R ClK Read PDE I I LI Read PTE FIGURE 5 17 TLB Miss 4 Kbyte Page Bus Cycle Timing I I Read PTE I Write PTE L L _ ___ I Read that caused I TLB miss 5 173 ...

Page 293: ...shows the effect of BUFF intervening in a locked read write pair of bus cycles The example begins with the read while LUCK is asserted System logic asserts BUFF while the processor is asserting ADS for the write causing the pro cessor to abort the write and float its bus in the next clock Another bus master must wait two clocks after the assertion of BUFF before driving its first bus cycle because...

Page 294: ...al Reference Manual i r t t t t r J __l 4 r t r ti r O C 1J I i 063 00 I L d J r r r c J i ri r rl o II i I I I I I I I I I I I i I I I I I Read Aborted Write Restarted Write FIGURE 5 18 Locked Operation with DOFF Intervention Bus Cycle Timing 5 175 ...

Page 295: ...rrupt vector in D7 DO The interrupt vector is an offset into an interrupt table System logic must return a BRDY in response to both cycles The processor inserts at least one idle clock between the locked reads System logic will typically not be able to determine the instruction boundary on which the processor recognizes INTR Thus as a practical matter system logic should hold INTR asserted until t...

Page 296: ... In Figure 5 19B this appears as a burst read which is cached GDT Lookup Using the segment descriptor from the IDT the processor performs another read of the global descrip tor table GDT to look up the 8 byte code segment descrip tor This also appears as a burst read which is cached Alternatively this read can access the local descriptor table rather than the global descriptor table Write to Stack...

Page 297: ...H r r t H H I I I I 1 i IJh lh i I I I I I i i i I I Ii I I 4 r4i ir i_ i ii t t iii I I r i 1 H rH ri i Ii I I I I II I I I I r I I w R i i I I I i iii 11 CLK h h hhhh hhhh h hhhhh hhh hh h hh hhhhL LL LLLLLLLLh hhI l L L L L LJ LIl l l l LI L L L L L L L L Lt L L L Lt Lt Lt LI Ll Ll Ll Ll Ll Ll Ll Ll Ll Ll L INTR Asserted Interrupt Acknowledge Cycles FIGURE 5 19A Interrupt Acknowledge Operation ...

Page 298: ...ar1996 ClK A31 A3 llF7 lffii D63 DO INTR meR M fO WjR ClK I I IDT Lookup FIGURE 5 198 Interrupt Acknowledge Operation Part 2 Bus Cycle Timing AMD AMD5136 Processor Technical Reference Manual I I I GDTLookup 5 179 ...

Page 299: ...6 Processor Technical Reference Manual ClK A31 A3 CACHE OfC 063 00 INTR ClK I Write I to stack FIGURE 5 19 Interrupt Acknowledge Operation Part 3 5 180 18524BjO Mar1996 I Code fetch I for interrupt Bus Interface ...

Page 300: ...ion During the first cycle D31 DO carries the EIP value of the source branch instruction Dur ing the second cycle D31 DO carries the EIP value of the branch target instruction TABLE 5 23 Encodings For Special Bus Cycles BE7 BU A31 A3 Special Bus Cyelet Cause FEh OOh Shutdown Triple fault FDh OOh Cache Invalidation INVD instruction FBh 10h Stop Grant STPCr K FBh OOh Halt HLT instruction F7h OOh Cac...

Page 301: ...ferenti ated by BE7 BEO and A31 A3 In this example BE7 BEO FBh and A31 A3 0 so it is the special cycle the processor generates after executing a HLT instruction System logic must respond with BRDY All special bus cycles serialize the pipeline EWBE is not checked prior to running special bus cycles all of which have WIR 1 so EWBE has no effect on any special bus cycles 1 X I X I Y r FIGURE 5 20 Bas...

Page 302: ...sor encoun ters such a triple fault it stops its activity on the bus and gen erates the special bus cycle for shutdown BE7 BEU FEh System logic must respond with BRDY System logic must assert NMI INIT RESET or sm to get the processor out of the Shutdown state ClK A31 A3 BE7 BEO ViffiE O C 063 00 INTR MjID W R ClK ch I i i L I I I J I ch I i i I I I I I 117 I kW W I I JJJJJJ h I Shutdown I Occurs I...

Page 303: ...boundary ClK A31 A3 ID BEO tAmE o C 063 00 FIlJ5II KEN IOCR M IU W R ClK FLUSH causes the processor to write back all modified lines in its data cache Only one such writeback is shown in this exam ple After all writebacks complete the processor invalidates all lines in both of its caches Then the processor generates the FLUSH acknowledge special bus cycle BE7 BEU EFh to indicate that the writeback...

Page 304: ...e bus the lack of activity on the bus as the microcode invalidates the lines in the internal cache can be seen When all lines in both caches are invalidated the processor drives the cache invalida tion special bus cycle BE7 BEU FDh System logic must respond by asserting BRDY When it does the processor typi cally begins driving one or more burst reads on the bus to refill its caches D63 DO f 1 I J ...

Page 305: ... cache line is in the modified state the line is written back immediately before being invalidated During such writebacks A31 A5 defines the address of a 32 byte location in memory to which the modified cache line will be written back After all modified lines are written back and all lines in both caches are invali dated the processor first drives the cache writeback and inval idation special bus ...

Page 306: ... lffij D C D63 DO WCK M ro W R ClK AMD AMD5 6 Processor Technical Reference Manual I I Cache Writeback and invalidation special cycle FIGURE 5 24B Cache Writeback and Invalidation Cycle WBINVD Instruction Part 2 Bus Cycle Timing 5 187 ...

Page 307: ...nd system logic must respond by asserting BRDY to each of the cycles The first cycle identifies the branch source and the second identifies the branch target as shown in Table 5 24 TABLE 5 24 Branch Trace Message Special Bus Cycle Fields Signals First Special Bus Cycle Second Special Bus Cycle A31 0 first special bus cycle source 1 second special bus cycle target Operating Mode of Target 11 Virtua...

Page 308: ...18524B O Mar1996 elK A31 A3 CArnE DfC D63 DO FIGURE 5 25 Branch Trace Message Cycle Bus Cycle Timing AMD AMD5 6 Processor Technical Reference Manual I Branch trace I Message special cycles 5 189 ...

Page 309: ... was asserted the processor completes the bus cycle and waits until the system asserts the last expected BRDY and also asserts EWBE In Figure 5 26A a burst read is shown completing after sm is asserted 3 Acknowledge After sampling EWBE asserted the proces sor asserts SMIACT to acknowledge the interrupt This is visible on the bus after sm is recognized At that point sys tem logic must ensure that a...

Page 310: ... I i j i i i I I I i r i I I i i i I I i I I i I I Ill I I o tf 111 I i I I I I I I i I I I I 063 00 i i i I I I I I MjlO SMI W R I I 1 J i 1 i I I I I I l J I 11 I H IH iH I H Ir I i I 1 I i I I i i eLK thhh h h hhhh hhhhhhhnhn hh 5MI Asserted Asserted RGURE 5 26A Transition from Normal Execution to SMM Part 1 Bus Cycle Timing 5 191 ...

Page 311: ... D63 DO OCR M ID SM1 SMIACT w R ClK I I I I 1 IL 1 rL j il il IL 1 il n h h 1L FIGURE 5 268 Transition from Normal Execution to SMM Part 2 5 192 I I I V I I I I 1 1 I I I I i I I I I I I I i i i h i 1 I I I I I r I r I I I 1 1 I r I i I I I II I I I i I I I I I i rm fLlLn I g sss es te Bus Interface ...

Page 312: ...as or at sometime after it asserts STPCLK In Figure 5 27A a burst read is shown completing after StPCLK is asserted 3 Stop Grant Cycle After sampling both EWBE asserted the processor drives a Stop Grant special bus cycle This cycle is identified by DiC 0 Mtm 0 WfR 1 BID BEn FBh and A31 A3 10h System logic must respond by asserting BRDY This is visible on the bus near the middle of Figure 5 27A 4 S...

Page 313: ...rt I I i l BEl BED i 1 I H i i 1r H H H H r rV I i 1 I In I if i I i i H H i o Ct n Vl 1 I i 063 00 H I H H r r iV I I I i t H I i_ I t H I r t r H I I i H H I I I r H H H H lJr i W R ClK State I I 5TPITK Stop Grant I Asserted I Special Cycle FIGURE 5 27A Stop Grant and Stop Clock Modes Part 1 5 194 Bus Interface ...

Page 314: ...r Technical Reference Manual I t i i i I I i JII i i I I I i IrrH i I 1 I r i I i l i r m II I I i i i elK rtrt rJJJLrLill rtrthrt nMh JiliULn_UlrVu Normal I State FIGURE 5 278 Stop Grant and Stop Clock Modes Part 2 Bus Cycle Timing 5 195 ...

Page 315: ...e The 286 processor does not have an INIT input a transition from Protected mode to Real mode can only be made on the 286 processor by asserting RESET With the INIT signal however the operating system can cause the transition through a BIOS interrupt without loss of cache contents or floating point state Upon recognizing an INIT interrupt at the next instruction retirement boundary the processor p...

Page 316: ...E D C D63 DO INIT M RJ RESET W R ClK I I INIT Asserted AMD AMD5J116 Processor Technical Reference Manual I _ r I i i i I Code fetch from FFFF_FFFOh FIGURE 5 28 INIT Initiated Transition from Protected Mode to Real Mode Bus Cycle Timing 5 197 ...

Page 317: ......

Page 318: ...ers both to the pro cessor s internal clock and to the bus clock CLK Thus each type of clock is explicitly differentiated in the descriptions that follow 6 1 Memory Memory The processor can be configured for memory bus speeds of 50 60 or 66 MHz Main memory can be built from Page mode or EDO extended data out DRAM On a 66 MHz bus the read cycle time for a page hit in EDO DRAM is 7 2 2 2 7 clocks fo...

Page 319: ...d ware the boot address at FFFF_FFFOh which is accessed when RESET or INIT is asserted and the default addresses for SMM However other physical memory mapping requirements are imposed by BIOS the operating system and the specific hardware implemented for the system In general the conven tions for hardware memory mapping for DOS based desktop systems include the following Memory decoder aliasing of...

Page 320: ...byte 1 1 000 F_FFF F 1 _ _ _ _ _ _ BIOSROM Device ROM Memory Mapped I O 640 Kbyte DOS Kernel BIOS Data Aliased Boot ROM High Memory Low conventional Memory OOOF_COOO ______ J I I I I I BIOS Remap During Boot 0003 FFFF SMM __ J 0003_8000 Memory InterruptVeclors 0000_0000 _ Decimal Hexadecimal FIGURE 6 1 Typical Desktop System BIOS Memory Map Memory 6 1 ...

Page 321: ...address OOOF_FFFOh When RESET or INIT is asserted however the left shift is not done and the high 16 address bits are all set to 1 yielding the physical address FFFF_FFFOh Thereafter address translation only begins to work in the normal Real mode manner when the first far jump is executed This jump loads the code segment regis ter with a 16 bit segment selector and this selector load causes the ad...

Page 322: ...s in this region and BIOS uses some of the RAM in this region to address locations that should not be cached such as memory mapped 110 ports video disk net work and other devices Thus system logic typically does not assert KEN during accesses to high memory System logic can of course drive KEN so as to specify any other areas of memory as non cacheable although this is nor mally not done SMM Memor...

Page 323: ...ze it with configuration parameters and the SMM service routine Thereafter the IOS typically remaps the area from its default location in low memory to high or extended memory as shown in Figure 6 1 After the remapping by BIOS the address decoder must allow only the processor to access the SMM memo ory area Other bus masters must be prevented from accessing it unless the system design specifically...

Page 324: ...SMM Base Address CS 1 0003_0000 FIGURE 6 2 Default SMM Memory Map Memory System logic controls the cacheability of SMM memory with KEN in the same way that it controls the cacheability of mem ory space If SMM memory is to be non cacheable KEN must be held negated from when SlVII is asserted until SMIACT is negated If SMM memory is to be cacheable KEN must be asserted for cacheable read cycles 6 7 ...

Page 325: ...that memory accesses in SMM do not hit locations cached from main memory If SMM memory is to be cacheable FLUsH must also be asserted with Sl I when entering SMM and the SMM service routine must execute the WBINVD instruction to invalidate the caches just prior to executing the RSM instruc tion which returns the processor from SMM The use of FLUsH or WBINVD adds potentially significant time to the...

Page 326: ...any line in the L1 cache is guaranteed to be in the L2 cache The first principle L2 cache bigger guarantees that the L2 cache will have data that is not already in the L1 cache The second principle L2 cache line size greater or equal to L1 cache line size can simplify and speed up transfers from the L2 cache to the L1 cache The third principle inclusion can simplify and speed up cache coherency si...

Page 327: ... and writes are given in Table 2 2 on page 2 19 Complete descrip tions of the signals that control cacheability and cache coher ency are given on the following pages CACHE Section 5 2 15 on page 5 50 EAD S Section 5 2 20 on page 5 59 HIT Section 5 2 25 on page 5 72 IITl M Section 5 2 26 on page 5 74 INV Section 5 2 33 on page 5 89 KEN Section 5 2 34 on page 5 90 PCD Section 5 2 39 on page 5 100 PW...

Page 328: ... 18 on page 5 136 The PWT bit also enters into this control but it is written by the operating system rather than system logic Alternatively system logic can force the on chip data cache to statically observe a writethrough or a writeback protocol by tying WBIWT as follows Writethrough Protocol Tie WBIWT Low Writeback Protocol Tie WBIWT High In the writethrough protocol a cache line is either in t...

Page 329: ...to cache all cacheable reads in the exclusive state and all cacheable writes update only the cache In systems with multiple caching mas ters WBIWT can be generated after inquire cycles to all other caching masters by the logical OR of HIT from all of the mas ters This allows the processor to cache reads in the exclusive or modified state only if no other master has a copy The write once protocol a...

Page 330: ... instruction or data cache or it asserts both HIT and HITlVI if the address matches a modified line in the data cache If HITlVI is asserted the processor writes the modified line back to memory If INV was asserted with EAIJS a hit invalidates the line If INV was negated with EAIJS a hit leaves the line in the shared state or transitions it from the modified to shared state On the AMD5K86 processor...

Page 331: ...ugh information to cache that line in the exclusive state this requires that HIT be monitored Lookaside caches must implement a signal with which to inform the memory controller that a processor access or an inquire cycle hit the L2 cache so as to disable the memory from responding A version of HIT can be implemented for this purpose Inquire cycle logic in systems with a look through L2 cache norm...

Page 332: ...le caching masters For example if Master A controls the bus and attempts to write a memory location that is cached by Master B in a modified state a shared L2 controller could drive an inquire cycle to Master B forcing a writeback But Master B cannot write back until Master A is off the bus In this case the L2 controller could use IIITM from Master B to gate the asser tion of BUFF to Master A Syst...

Page 333: ... processor can write back its modified line to main memory and the shared L2 cache j 1lOFF Other G E7iD5 Caching Master DHITM 0 Vwriteback 1lOFF Processor Bus V V Look Aside System Main UCache Logic Memory System Bus FIGURE 6 3 DOFF Example 6 16 A configuration in which both caching masters were on oppo site sides of a shared L2 look through cache would have some what similar operations except tha...

Page 334: ... logic from the L2 cache controller Figure 6 4 shows such a design A typical sequence for inquire cycles that hit modified lines in the processor s cache might be as follows 1 The master on the system bus requests access to memory 2 System logic responds by asserting BUFF to the processor s L2 cache controller 3 System logic drives an inquire cycle represented by EADS to the L2 controller 4 The L2...

Page 335: ... 18524B O Mar1996 G Writeback AMD5K86 I Processor FllTM D AHOLD 0EAlJ5 Look Through L2 cache Fl1TM U OOFF0 G EAlJ5 System Logic II 2 MemoryAccess System Bus JJ G OOFF Main Other Memory Bus Master FIGURE 6 4 AHOLD and DOFF Example 6 18 System Design ...

Page 336: ...can have the data exclusively and other caching masters must invalidate their copies The protocol allows other masters to determine whether the processor has a modified line in its Ll cache by driving an inquire cycle to the L2 cache and it allows other masters via inquire cycles to intervene in the processor s exclusive use of the data Figure 6 5 shows an example System logic drives separate WBJ ...

Page 337: ...e WBfWT input has no effect This leaves the Ll and L2 caches as follows Ll cache line in the modified state L2 cache line in the modified state 5 During all subsequent writes to that line the processor sim ply updates its modified line Inquire cycles to the L2 cache that occur between Steps 1 and 3 get a mT but not a HITlVI thus avoiding the need to drive simultaneous or subsequent inquire cycles ...

Page 338: ...ference Manual o line Fill o WB wr O CDWritethrough AMD5K86 CD WB wr O CD Writethrough Processor CD WB wr l D o WB wr O Look Through CD WB wr l UCache U System Logic II System Bus jJ Main Other Memory Bus Master FIGURE 6 5 Write Once Protocol Cache 6 21 ...

Page 339: ...validations are typically performed by the operating system or system logic during task or mode changes The invalidations are described on pages 5 67 and 5 181 The MESI state transitions for cache invalidations are given in Table 2 3 on page 2 20 MoM Masking of Cache Accesses The processor samples A 2UM only in Real mode and applies A 2UM masking to its linear cache tags through which all pro gram...

Page 340: ...utine It is designed for power management and other system control activities that can occur transparently to conventional operating systems like DOS and Windows The code and data for SMM are stored in an SMM memory area that should be separate from main memory The processor enters SMM when system logic asserts the SMI interrupt and the processor acknowledges it with SMIACT at which point the proc...

Page 341: ...upt vectors use the Real mode interrupt vector table but see Section 6 3 8 on page 6 32 The IF flag in EFLAGS is cleared INTR not recognized The NMI interrupt is disabled The TF flag in EFLAGS is cleared single step traces dis abled Debug register DR7 is cleared debug traps disabled Figure 6 2 on page 6 7 shows the default map of the SMM mem ory area It consists of a 64 Kbyte area between 0003_000...

Page 342: ...s are unmodified CR4 OOOO_OOOOh GDTR Unmodified LDTR Unmodified IDTR Unmodified TR Unmodified DR7 Unmodified DR6 Undefined 6 3 2 SMM State Save Area When the processor acknowledges an sm interrupt by assert ing SMlACT it saves its state in the 512 byte SMM sta e save area shown in Table 6 2 The save begins at the top of the SMM memory area SMM Base Address FFFFh and fills down to SMM base address ...

Page 343: ...nly FFCO LDTR 16 upper 16 reserved read only FFBC GS 16 upper 16 reserved read only FFB8 FS 16 upper 16 reserved read only FFB4 DS 16 upper 16 reserved read only FFBO SS 16 upper 16 reserved read only FFAC CS 16 upper 16 reserved read only FFA8 ES 16 upper 16 reserved read only FFA4 110 Trap Dword 32 See Section 6 3 6 read only FFAO reserved 32 FF9C 110 Trap EIP 32 read only FF98 reserved 32 FF94 ...

Page 344: ...d read only FF50 DS Attributes 12 upper 20 reserved read only FF4C DS Base 32 read only FF48 DS Limit 20 upper 12 reserved read only FF44 SS Attributes 12 upper 20 reserved read only FF40 SS Base 32 read only FF3C SS Limit 20 upper 12 reserved read only FF38 CS Attributes 12 upper 20 reserved read only FF34 CS Base 32 read only FF30 CS Limit 20 upper 12 reserved read only FF2C ES Attributes 12 upp...

Page 345: ...re available on the processor The SMM revision identifier fields are as follows Bits 31 18 reserved Bit 17 SMM base address relocation always 1 enabled Bit 16 1 0 trap restart always 1 enabled Bits lS 0 SMM revision level 0000 These fields are the same as in the Pentium processor Unlike the Pentium processor however the liD trap restart and the SMM base address relocation functions are always enab...

Page 346: ... with the Pentium processor s analogous feature The following pseudo code implements a relocatable SMM base address in BIOS begin if SMI Handler is to be Relocated then set SMM Base Address offset FEF8h to new value resume else end SMM execution to begin at relocation area resume To relocate the SMM base address above the 1 Mbyte limit imposed by Real mode segment addressing use the address overri...

Page 347: ...alt state Before return from SMM the halt restart slot can be written as Bits IS I Undefined Bit O Point of return from SMM 1 return to Halt state 0 return to state specified by SMM state save area The fields of the halt restart slot are the same as in the Pen tium processor auto halt restart slot During entry into and exit from SMM the processor writes or reads only bit 0 of the 16 bit value alth...

Page 348: ...trapped I O instruction should be re executed on return from SMM This is sometimes called the liD instruction restart func tion Re executing a trapped I O instruction is useful for exam ple if an I O write to disk finds the disk powered down The system logic monitoring such an access can assert sm Then the SMM service routine would query system logic find a failed I O write take action to power up...

Page 349: ...arted then if valid liD instruction test offset FFA4 then set liD restart slot offset FFOO to OOFFh end During a simultaneous s MI IIO instruction trap and debug breakpoint trap the AMD5K 86 processor first responds to the SMI and postpones writing the exception related information to the stack until after the return from SMM via the RSM instruction If debug registers DR3 DRO are used in SMM they ...

Page 350: ...terrupt All other exceptions and interrupts within SMM are fully compatible with those supported by the Pentium processor in SMM The IF flag in EFLAGS is cleared automatically when the pro cessor enters SMM thus disabling maskable interrupts The HLT instruction should not be executed in SMM without first setting the IF bit Table 5 2 on page 5 9 and Table 5 3 on page 5 17 summarize the behavior of ...

Page 351: ...sion would be communicated to the power man agement logic which would assert sTpcLK to the processor and optionally stop driving CLK to the processor and other logic For details on sm and STPCLK see pages 5 117 and 5 123 respectively State Transitions The five states in the processor s clock control protocol as shown in Figure 6 6 are as follows Normal Execution Real mode Virtual 8086 mode Protect...

Page 352: ... phase lock loop still runs its key internal logic is still clocked most of its inputs and outputs retain their last state except D63 DO and DP7 DPO which are floated and it still responds to input sig nals The HLT instruction is commonly executed by modern UNIX type operating systems as a method of entering an idle loop The operating system sees that it has no pending processes therefore nothing ...

Page 353: ...ted Real RESET SliilI INIT Virtual 8086 5TPITK Negated or INTR Asserted Protected or RESET Asserted SMM 5TPITK Asserted 5TPITK Negated 1 I fAIJS Stop Grant fAIJS Halt Inquire Stop Grant State State State ClK ClK Started Stopped Stop Clock State FIGURE 6 6 Clock Control State Transitions 6 16 System Design ...

Page 354: ...state the majority of the processor s internal clock distribution and all internal pullup resistors are disabled However its phase lock loop still runs its key internal logic is still clocked most of its inputs and outputs retain their last state except D63 DO and DP7 DPO which are floated and it still responds to input signals Stop Grant Inquire State An inquire cycle driven while the processor i...

Page 355: ...K can be driven with a different frequency and or the bus to processor clock ratio can be changed on the BF input upon restarting CLK Clock Control Compatibility with Pentium Processor The differences in clock control functions between the AMDSK 86 and Pentium processors are described in Section A S on page A 12 5 Power and Ground Design 6 38 All of the processor input signals operate at 3 V excep...

Page 356: ...esign recommendations apply to power con nections between the processor and the system board Connect all Vee pins to a Vcc plane on your system board Connect all Vss pins to a GND plane on your system board Do not drive address and data buses into large capacitive loads at high frequencies This can cause transient power surges Decouple capacitance near the processor Use low inductance capacitors a...

Page 357: ...ormal operating level and PWRGOOD is asserted Figure 6 7 shows this timing After Vee and CLK reach specification RESET must be asserted for a minimum of 1 ms to allow the digital phase lock loop to syn chronize Vcc_ _ vee at Operating Voltage PWRGOOD I RESET must be asserted 1ms for at least 1msafterVcc and QK are stable RESET elK FIGURE 6 7 Vee and elK 6 40 System Design ...

Page 358: ... Figure 6 10 illustrates a clamping circuit that grounds CPUCLK for a predetermined time The clock clamping circuit shown in Figure 6 10 has several advantages In addition to delaying CPUCLK until Vee has reached specification it also prevents noise glitches on the clock signal from being sensed by the processor during this time Noise glitches are typically caused by poor design of the clock gener...

Page 359: ...utput Enable CPUClK in from Core logic Chip Vee to CPU 3 3 V 5V or other Ground to Core logic R3 lOOK r I CRI CR2 I L _ _ _ FIGURE 6 10 CPUClK Clamping Circuit 6 42 Rl 33n R2 10K 0 001 IlF 18524B O Mar1996 ClK To System 1kn WRGOOD P CPUClK Out to CPU 022N7002 N Channel MOSFET Ground to CPU System Design ...

Page 360: ...ance ESR ratings at high frequencies and a minimum voltage rating of 6 V for all other capacitor values Place some capacitors very near to the processor prefer ably on the inside perimeter of the processor socket Connect bypass capacitors on the top side of the PCB di rectly to the processor s power pins Multilayer Printed Circuit Boards Use a minimum of four layers one split power plane one groun...

Page 361: ... In general the trade off is heat sink size and cost versus airflow quantity and temperature A small low cost heat sink requires more airflow than a larger more efficient heat sink Such cooling products are widely available For detailed speci fications and assistance is selecting a product contact your AMD field application engineer or browse the AMD home page on the World Wide Web see Section 6 8...

Page 362: ...ations 6 8 Design Support and Peripheral Products AMD field application engineers FAEs can help you solve system design problems and select peripheral products that are compatible with the AMD5K86 processor You can locate the FAE nearest you by contacting one of the AMD offices listed in this manual You can also find support information on AMD s World Wide Web pages A list of available Web infor m...

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Page 364: ...e AMDSK 86 processor to float all of its output and bidirectional signals Cache and TLB Testing The Array Access Register AAR supports writes and reads to any location in the tag and data arrays of the processor s on chip caches and TLBs Debug Registers Standard 486 debug functions with an 110 breakpoint extension Branch Tracing A pair of special bus cycles can be driven immediately after taken br...

Page 365: ...llection of signals registers and processor microcode that is enabled when external debug logic drives RIS Low or loads the AMD5K 86 processor s Test Access Port TAP instruction register with the USEHDT instruction The test related signals and their descriptions include the fol lowing FLUSH Page 5 67 FRCMC Page 5 70 ERR Page 5 80 INIT Page 5 82 PRDY Page 5 104 RIS Page 5 108 RESET Page 5 110 TCK P...

Page 366: ...ation bits that enable cache branch tracing debug and clock control func tions The WRMSR and RDMSR instructions access the HWCR when the ECX register contains the value 83h as described in Section 3 3 5 on page 3 35 Figure 7 1 and Table 7 1 show the format and fields of the HWCR DDC DIC DBP DC 876 543 2 1 a III I 001 Enable branch trace usages 100 Activate Probe mode on debug trap Disable Stopping...

Page 367: ...on Disables branch prediction J o enabled 1 disabled 4 reserved Debug control bits 000 Off disable HWCR debug control 001 Enable branch tracing messages See Section 7 6 on page 7 17 010 reserved 3 1 DC Debug Control 011 reserved 100 reserved 101 reserved 110 reserved 111 reserved Disable Stopping Disables stopping of internal processor 0 DSPC Processor Clocks clocks in the Halt and Stop Grant stat...

Page 368: ... the BIST EADS should not be asserted during a BIST The processor accesses the physical tag array during BISTs and these accesses can conflict with inquire cycles 7 2 1 Normal81ST Built In Self Test BIST The normal BIST is invoked if INIT is asserted at the falling edge of RESET The BIST runs tests on the internal hardware that exercise the following resources Instruction cache Linear tag director...

Page 369: ...T Error Bit Definition in EAX Register Bit Bit Value Number 0 1 31 9 No Error Always 0 8 No Error Data path 7 No Error Instruction cache instructions 6 No Error Instruction cache linear tags 5 No Error Data cache linear tags 4 No Error PLA 3 No Error Microcode ROM 2 No Error Data cache data 1 No Error Instruction cache physical tags 0 No Error Data cache physical tags Test Access Port TAP BIST The...

Page 370: ...oard traces and connections can be tested for integrity and driveability The Output Float Test mode can only be exited by asserting RESET again On the AMD5K86 and Pentium processors FLUSH is an edge triggered interrupt On the 486 processor however the signal is a level sensitive input 7 4 Cache and TLI Testing Output Float Test Cache and TLB testing is often done by the BIOS or operating system du...

Page 371: ...a to be read or written The WRMSR and RDMSR instruc tions access the AAR when the ECX register contains the value 82h as described in Section 3 3 5 on page 3 35 Figure 7 2 shows the format of the AAR 0 Array Pointer I Contents of EDX MSR 0 82h Array Data I Contents of EAX FIGURE 7 2 Array Access Register AAR 7 8 To read or write an array location perform the following steps 1 ECX Enter 82h into EC...

Page 372: ... bits For the 4 Kbyte TLB the way and set specify one of the 128 TLB entries For the 4 Mbyte TLB one of only four entries is speci fied Bits 7 0 of every array pointer encode the array D which iden tifies the array to be accessed as shown in Table 7 3 To sim plify multiple accesses to an array the contents of EDX is retained after the RDMSR instruction executes EDX is nor mally cleared after a RDM...

Page 373: ...ample in Figure 7 3 top the array pointer in EDX spec ifies a way and set within the data cache linear tag array Elh in bits 7 0 of the array pointer or the physical tag array ECh in bits 7 0 of the array pointer If the linear tag array Elh were accessed the data read or written includes the tag and the status bits The details of the valid fields in EAX are pro prietary 19 18 13 12 Set Valid Bits ...

Page 374: ... Pointer 31 30 29 28 27 19 18 Set EAX Test Data 31 Valid Bits EOh Data FIGURE 7 4 Test Formats Data Cache Data Cache and TLB Testing AMDl1 AMD5 J6 Processor Technical Reference Manual 13 12 10 9 8 7 Dword Array 10 EOh o o I 7 11 ...

Page 375: ... 28 27 20 19 12 11 8 7 o Set ArraylD ESh EDh E6h E7h EAX Test Data 31 20 19 0 Valid Bits ESh Linear Tag 31 21 20 0 Valid Bits EDh Physical Tag 31 19 18 0 Valid Bits E6h Valid Bits 31 19 18 0 Valid Bits E7h Branch Prediction Bits FIGURE 7 5 Test Formats Instrudion Cache Tags 7 12 Test and Debug ...

Page 376: ... 29 28 27 20 19 Set EAX Test Data 31 26 25 E4h Instruction Bytes AMD AMD5xB6 Processor Technical Reference Manual 12 11 9 8 7 Valid Bits Opcode Bytes ArraylD E4h o o FIGURE 7 6 Test Formats Instruction cache Instructions Cache and ns Testing ...

Page 377: ...ual EDX Array Pointer 31 30 29 28 27 EAX Test Data 31 22 21 E8h Hbyte Page and Status 31 20 19 E9h 4 Kbyte linear Tag AGURE 7 7 Test Formats 4 Kbyte TLB 7 14 13 12 8 7 Set Valid Bits Valid Bits 18524BjO Mar1996 Array ID E8h E9h o o o Test andDebug ...

Page 378: ...8 27 EAX Test Data 31 EAh 4 Mbyte Page and Status 31 EBh 4 Mbyte Linear Tag FIGURE 7 8 Test Formats 4 Mbyte TLB Cache and TLB Testing AMD AMDSIJ6 Processor Technical Reference Manual 12 11 15 14 8 7 ArraylD EAh EBh Valid Bits Valid Bits o o o 7 15 ...

Page 379: ...o embed breakpoints in code and allow debugging of ROM as well as RAM For details on the standard 486 debug functions and registers see the AMD documentation on the Am486 processor or other commercial x86 literature 1 0 Breakpoint Extension The processor supports an I O breakpoint extension for break points on I O reads and writes This function is enabled by set ting bit 3 of CR4 as described in S...

Page 380: ...ng Branch Tracing Branch tracing is enabled by writing bits 3 1 with 00lb and set ting bit 5 to 1 in the Hardware Configuration Register HWCR as described in Section 7 1 on page 7 3 When thus enabled the processor drives two branch trace message spe cial bus cycles immediately after each taken branch instruc tion is executed Both special bus cycles have a BID BED encoding of DFh 1101_1111b The fir...

Page 381: ...y Checking mode as the checker and reports checking errors on the IERR output If FRCMC is negated at RESET the processor operates normally although it also behaves as the master in a functional redundancy checking arrangement with a checker In the Functional Redundancy Checking mode two processors have their signals tied together One processor the master operates normally The other processor the c...

Page 382: ...rors The particular type of error or the instruction causing an error is not reported The arrangement works because the processor is entirely deterministic Speculative prefetching speculative execution and cache replacement all occur in identical ways and at identical times on both processors if their signals are tied together so that they run the same program The Functional Redundancy Checking mo...

Page 383: ...m the processor boundary The register is controlled with the EXTEST and SAMPLE in structions Device Identification Register DIR Contains the codes for manufacturer s identification part number and ver sion Bypass Register BR A path between TDI and TDO used to transfer test data to and from other board com ponents when no test operation is being performed by the processor Hardware Debug Tool Regist...

Page 384: ...roller exits the update state update_DR or updatejR The sections below describe only those aspects of the IEEE standard that are implemented uniquely by the AMD5K 86 pro cessor For a description of the IEEE mandatory TAP functions and the IEEE optional functions implemented by the AMD5K 86 processor see the IEEE Standard Test Access Port and Boundary Scan Architecture IEEE 1149 1 1990 specificatio...

Page 385: ...bed below Any instruction encodings not shown in Table 7 6 select the BYPASS instruction TABLE 7 6 Public TAP Instructions Instruction Encoding Register Description EXTEST 00000 BSR As defined by the IEEE standard SAMPLEI 00001 BSR As defined by the IEEE standard PRELOAD meODE 00010 DIR As defined by the IEEE standard lllGHZ 00011 BR As defined by the IEEE standard ALL1 00100 BR Forces all outputs...

Page 386: ...ls regis ters and processor microcode that is enabled when external debug logic drives RiS Low or loads the processor s Test Access Port TAP instruction register with the USEHDT instruction Documentation on the HDT is available under nondisclosure agreement to test and debug developers For information con tact your AMD sales representative or field application engi neer Hardware Debug Tool HOT 7 2...

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Page 388: ... software In particular the following AMDSK 86 processor fea tures are compatible with the Pentium processor Package and pinout Electrical interface including bus cycles AC and DC parameters interrupt handling power saving etc Instruction set programming model memory management etc Because the AMDSK 86 processor takes a different approach to implementing the x86 architecture there are a few subtle...

Page 389: ... x x Address Strobe AIJSC x x Address Strobe AHOLD x x Address Hold AP x x Address Parity APCHK x x Address Parity Check APICEN x APIC Enable High during RESET PICD1 x PIC Data 1 BE7 BEU x x Byte Enables Flush 4 x Dual Processor Flush APICID3 APICIDO x APIC ID duringreset BF x x Bus to Core Frequency Ratio BOFF x x Bus Backoff BP3 BP2 x Breakpoint 3 to 2 BP1 BPOI Breakpoint 1 to 0 or PM1 PMO x Per...

Page 390: ...RR x x Floating Point Error x x Float Test Mode during RESET FLUSH x x Writeback and Invalidate Caches Functional Redundancy Checking Mas FRCMC x x ter Checker IIIT x x Inquire Hit IIITIJ x x Inquire Hit to Modified Line HLDA x x Hold Acknowledge HOLD x x Hold ERR x x Internal Error IGNNE x x Ignore Numeric Error x x Execute BIST during RESET INIT x x Initialize warm start INV x x Invalid or Share...

Page 391: ...to Modified Line PICCLK x PIC clock 5 V Tolerant PRDY x x Probe Ready PWT x x Page Writethrough RIS x x Run or Stop RESET x x Reset SCYC x x Misaligned Transfer SID x x System Management Interrupt SMIACT x x System Management Interrupt Active STPCLK x x Stop Clock TCK x x Test Access Port TAP Clock TDI x x Test Access Port TAP Data In TDO x x Test Access Port TAP Data Out TMS x x Test Access Port ...

Page 392: ...rites will follow The Pentium processor performs two unlocked reads to get the descriptor If the Accessed bit needs to be set two locked reads will be followed by one i byte locked write For updates to the Busy bit in the TSS descriptor the AMD5K 86 processor behaves in the manner described for updates to the Accessed bit The Pentium processor does not perform the unlocked read to get the descript...

Page 393: ...m processor Split 110 write cycles occur in the same order on both processors Halt Cyde after FLUSH When halted the AMD5K 86 processor reruns a Halt special cycle after the Flush Acknowledge special cycle following a cache flush operation The Pentium processor does not rerun a Halt special cycle Selectable Drive Strengths on Output Driver The AMD5K86 processor supports selectable drive strengths o...

Page 394: ... follows Drive Strength BRDYC BOSCHK Pentium Strength 1 weakest 1 X Strength 2 medium 0 1 Strength 3 strongest 0 0 AMD5K 86 Strength 1 weak 1 X Strength 1 weak 0 1 Strength 2 strong 0 0 The exact drive characteristics of the two strengths differ from the Intel parts Those differences are not documented in this functional description See the AMD5K 86 processor data sheet for more information A l ...

Page 395: ...pin In treating the snoop as a miss the Pentium processor deas serts the HIT pin and caches the line based on KEN WBIWT and PWT in the same way it does for linefills with no snoop The behavior of snoops to the linefill buffer after cacheability is determined is described in Section A 3 2 BUFF Asserted before Snoop to Linefill Buffer and after the Cacheability of the Line is Established A snoop to ...

Page 396: ...he same line before the write appears on the bus the Pentium processor generates a snoop hit until the write is on the bus The AMD5K 86 processor generates a snoop miss in the window between when the cache is invalidated and the write appears on the bus The ICACHE line is invalidated in both processors by the time the write appears on the bus Invalidations during a FLUSH WBINVD During a FLUSHlWBIN...

Page 397: ...s to the same line change the state of the line from exclusive to modified and do not go external Both the AMD5K 86 and Pentium processors behave in this manner However if two or more writes to different locations within the same cache line are queued up in the store buffer the line is shared and the WBIWT pin is set High then the AMD5K 86 pro cessor correctly allows the first write to reach the b...

Page 398: ...bit being set for a page that is not actually used The AMD5K86 processor does not perform spec ulative TLB refills Page Fault Encountered by a Load Store Type of Instruction On a read page fault encountered by a load op store type of instruction the error code reported by a 486 processor indi cates a read operation whereas the Pentium processor indi cates a write operation The AMD5K86 processor re...

Page 399: ...akpoint trap the AMD5K 86 processor responds to the SMI first and postpones writing the fault frame for the debug trap to the stack until after the resumption of normal execution via RSM If debug registers DR3 DRO are going to be used while in SMM they must be saved and restored by the SMM software DR6 and DR7 are automatically saved and restored This is similar to the Pentium processor behavior P...

Page 400: ...t in slightly different ways The Pentium processor takes the NMI request immediately after recognizing the INTR but before executing any instructions from the interrupt handler The AMDSK 86 processor takes the NMI request upon encountering the IRET in the interrupt handler In fact the AMDSK 86 pro cessor unmasks NMI when any IRET is encountered not just one associated with INTR With both processor...

Page 401: ...code fault The Pentium and 486 processors prioritize the limit violation fault Task Switch On a task switch the AMDSK 86 processor sets the busy bit of the incoming task after storing the outgoing TSS according to 486 and Pentium processor documentation The Pentium pro cessor sets the busy bit before trying to store the outgoing TSS If a fault occurs while trying to store the TSS the Pentium pro c...

Page 402: ...kpoint matches do not set multiple B bits in DR6 on the AMD5K 86 processor Simultaneous Debug Trap and Debug Fault If a debug trap associated with the completion of an instruc tion single step trap or load store breakpoint occurs at the same time as a debug fault instruction breakpoint on the next instruction the Pentium processor merges the two conditions into a single call to the debug handler s...

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Page 404: ... 172 DBP 7 4 DC 7 4 DDC 7 4 DE 3 3 Index AMD AMD5 6 Processor Technical Reference Manual DIC 7 4 dirty 5 172 DSPC 7 4 G 3 8 3 11 GPE 3 3 MCE 3 3 3 4 PS 3 8 3 11 PSE 3 3 PVI 3 3 3 24 TSC 3 27 TSD 3 3 3 27 VIF 3 13 3 15 VIP 3 13 3 15 VME 3 3 3 12 BUFF 5 9 5 38 5 163 5 165 5 174 6 15 Boot Address 5 83 5 111 5 196 Boundary Scan 5 128 5 129 5 130 5 131 5 132 Boundary Scan Test Access Port TAP 7 19 Bran...

Page 405: ... KEN 5 90 enabling 2 13 FLUSH 5 67 hits 5 9 inquire cycles 2 21 instruction 2 14 internal snooping 2 22 invalidation 2 20 5 89 6 22 invalidation cycles 5 36 5 181 invalidations 2 16 2 17 L2 6 9 6 19 line fills 2 17 5 150 2 18524BjO Mar1996 line fill buffers 2 23 locking 2 13 MESI state 2 16 2 18 5 73 5 106 5 135 5 136 6 10 organization and management 2 13 replacement 2 20 SMM memory 6 5 snooping 2...

Page 406: ...eger shift units 2 9 load store units 2 10 pipeline 2 4 speculative 2 10 timing 4 5 units 2 8 Index AMD AMD5 IJ6 Processor Technical Reference Manual External Interrupts 5 14 External Interrupts Signals 5 11 External Write Buffers 5 63 F Fastpath 2 7 Features 1 2 FERR 5 10 5 65 Fetch 2 6 Flags IF 5 87 undefined 4 2 VIF 3 13 3 15 VIP 3 13 3 15 Float Test 7 7 Floated Outputs BUFF 5 39 HLDA 5 76 Floa...

Page 407: ...ptimization 4 1 performance 4 1 prefixes 4 3 RDMSR 3 35 RDTSC 3 34 4 18524B O Mar1996 RSM 3 37 serializing 2 8 shifts 4 2 short forms 4 1 simple 4 1 stack 4 2 store 2 15 2 24 SYSCALL 3 4 SYSRET 3 4 test 7 22 USEHDT 5 104 5 108 7 23 WBINVD 5 36 5 181 WRMSR 3 35 x86 predecode 2 3 Integer Instructions 4 8 Integer Shift Units 2 9 Internal Architecture 2 1 Internal Errors 5 80 Internal Resistors 5 4 In...

Page 408: ... Model Specific Registers MSRs 3 25 MOV to from CR4 3 33 Index AMD AMD5J116 Processor Technical Reference Manual Move and Convert 4 3 MSRs 3 25 Multiplies 4 3 N NA 5 9 5 97 5 151 Next Address 5 97 NMI 5 11 5 16 5 17 5 98 Noise Reduction 6 43 Non Maskable Interrupts 5 98 Notation xv 4 5 Numeric Errors 5 81 o Opcodes reserved 3 38 Operands 4 2 aligned 5 115 alignment 5 139 Optimization 4 1 Output Fl...

Page 409: ...5 133 Real Mode transition from protected mode 5 196 References xviii Register file 2 12 Registers 6 18524B O Mar1996 AAR 7 8 CR4 3 2 3 33 debug 7 16 DR7 DO 7 16 EFLAGS 3 15 HWCR 7 3 MCAR 3 4 3 25 MCTR 3 4 3 26 model specific 3 25 MSRs 3 25 operands 4 2 state after RESET or INIT 5 111 TAP device ID 7 21 Reorder Buffer ROB 2 11 Reordering of Reads and Writes 2 27 Replacement buffer 2 25 cache 2 20 ...

Page 410: ...test 5 11 TMS 5 11 5 131 TRST 5 11 5 132 WIR 5 9 5 133 5 137 WBIWT 5 10 5 134 5 151 Signals PCHI 5 10 Simultaneous Interrupts 5 16 SMI 5 11 5 17 5 117 5 190 SMIACT5 9 5 11 5 122 5 190 SMM 5 117 5 122 6 23 base address 6 28 exceptions and interrupts in SMM 6 32 Halt restart 6 30 IJO restart 6 31 IJO trap dword 6 31 initial state 6 25 memory map 6 5 revision identifier 6 28 RSM instruction state sav...

Page 411: ...11 5 128 TDI 5 11 5 129 TDO 5 11 5 130 Terminology xvi Test 7 1 AAR 7 8 arrays 7 7 BIST 7 5 boundary scan 7 19 cache 7 7 clock 5 128 data input 5 129 1 8 18524B O Mar1996 data output 5 130 float 7 7 functional redundancy 7 18 HDT 7 23 HWCR 7 3 instructions 7 22 mode select 5 131 PRDY 5 104 R S 5 108 reset 5 132 TAP 7 19 TAP device ID 7 21 TLBs 7 7 Test Access Port TAP TCK 5 128 TDI5 129 TDO 5 130 ...

Page 412: ...EWER 2 26 110 5 147 MESI state 5 136 reordering 2 27 Index AMD AMD5 6 Processor Technical Reference Manual single transfer from memory 5 142 single transfer misaligned 5 148 strongly ordered 2 26 W R 5 133 Writethroughs xvii 2 18 2 19 2 20 5 106 5 134 6 10 WRMSR 3 35 9 ...

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