Texas Instruments DM38x DaVinci, User Manual

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Registers
439 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.37 clkc_rst Register (offset = 104h) [reset = 0h]
clkc_rst is shown in Figure 1-293 and described in Table 1-204 .
Soft Reset Register
Figure 1-293. clkc_rst Register
31 30 29 28 27 26 25 24
MAIN_RST Reserved VIP2_CHR_DS_2_RS
T
VIP1_CHR_DS_2_RS
T
VIP2_CHR_DS_1_RS
T
VIP1_CHR_DS_1_RS
T
NF_DP_RST
R-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
VIP2_SC_RST VIP1_SC_RST VIP2_CSC_RST VIP1_CSC_RST VIP2_VIP_RST VIP1_VIP_RST VIP2_DP_RST VIP1_DP_RST
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved SDVENC_RST DVO2_RST HDCOMP_RST HDMI_DVO1_RST IND_TRANS2_DP_R
ST
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
IND_TRANS1_DP_R
ST
COMP_DP_RST GRPX3_DP_RST GRPX2_DP_RST GRPX1_DP_RST AUX_DP_RST PRIM_DP_RST VPDMA_RST
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-204. clkc_rst Register Field Descriptions
Bit Field Type Reset Description
31 MAIN_RST R/W 0h
Reset for all modules in DSS Main Data Path
30-29 Reserved R 0h Reserved
28 VIP2_CHR_DS_2_RST R/W 0h Video Input Port 2 CHR_DS 2 Reset 1 = Reset Enable 0 = Reset
Disable
27 VIP1_CHR_DS_2_RST R/W 0h Video Input Port 1 CHR_DS 2 Reset 1 = Reset Enable 0 = Reset
Disable
26 VIP2_CHR_DS_1_RST R/W 0h Video Input Port 2 CHR_DS 1 Reset 1 = Reset Enable 0 = Reset
Disable
25 VIP1_CHR_DS_1_RST R/W 0h Video Input Port 1 CHR_DS 1 Reset 1 = Reset Enable 0 = Reset
Disable
24 NF_DP_RST R/W 0h Noise Filter Data Path Reset 1 = Reset Enable 0 = Reset Disable
23 VIP2_SC_RST R/W 0h Video Input Port 2 Scaler Reset 1 = Reset Enable 0 = Reset Disable
22 VIP1_SC_RST R/W 0h Video Input Port 1 Scaler Reset 1 = Reset Enable 0 = Reset Disable
21 VIP2_CSC_RST R/W 0h Video Input Port 2 CSC Reset 1 = Reset Enable 0 = Reset Disable
20 VIP1_CSC_RST R/W 0h Video Input Port 1 CSC Reset 1 = Reset Enable 0 = Reset Disable
19 VIP2_VIP_RST R/W 0h Video Input Port 2 VIP_PARSER Reset 1 = Reset Enable 0 = Reset
Disable
18 VIP1_VIP_RST R/W 0h Video Input Port 1 VIP_PARSER Reset 1 = Reset Enable 0 = Reset
Disable
17 VIP2_DP_RST R/W 0h Video Input Port 2 Data Path Reset 1 = Reset Enable 0 = Reset
Disable
16 VIP1_DP_RST R/W 0h Video Input Port 1 Data Path Reset 1 = Reset Enable 0 = Reset
Disable
15-13 Reserved R 0h Reserved
12 SDVENC_RST R/W 0h SD Video Encoder/RF Modulator Reset 1 = Reset Enable 0 = Reset
Disable
11 DVO2_RST R/W 0h DVO2 Video Encoder Reset 1 = Reset Enable 0 = Reset Disable
10 HDCOMP_RST R/W 0h HDCOMP (HD_VENC_A) Video Encoder Reset 1 = Reset Enable 0
= Reset Disable