Texas Instruments DM38x DaVinci, User Manual

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Registers
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380 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.7 intc_intr0_ena_set0 Register (offset = 30h) [reset = 0h]
intc_intr0_ena_set0 is shown in Figure 1-263 and described in Table 1-174 .
Interrupt0 Enable/Set Register 0
Figure 1-263. intc_intr0_ena_set0 Register
31 30 29 28 27 26 25 24
SDVENC_INT_ENA_
SET
DVO2_INT2_ENA_SE
T
DVO2_INT1_ENA_SE
T
DVO2_INT0_ENA_SE
T
Reserved DVO1_INT2_ENA_SE
T
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
23 22 21 20 19 18 17 16
DVO1_INT1_ENA_SE
T
DVO1_INT0_ENA_SE
T
VIP2_PARSER_INT_
ENA_SET
VIP1_PARSER_INT_
ENA_SET
Reserved DEI_FMD_INT_ENA_
SET
Reserved VPDMA_INT0_DESC
RIPTOR_ENA_SET
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
VPDMA_INT0_LIST7_
NOTIFY_ENA_SET
VPDMA_INT0_LIST7_
COMPLETE_ENA_SE
T
VPDMA_INT0_LIST6_
NOTIFY_ENA_SET
VPDMA_INT0_LIST6_
COMPLETE_ENA_SE
T
VPDMA_INT0_LIST5_
NOTIFY_ENA_SET
VPDMA_INT0_LIST5_
COMPLETE_ENA_SE
T
VPDMA_INT0_LIST4_
NOTIFY_ENA_SET
VPDMA_INT0_LIST4_
COMPLETE_ENA_SE
T
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
VPDMA_INT0_LIST3_
NOTIFY_ENA_SET
VPDMA_INT0_LIST3_
COMPLETE_ENA_SE
T
VPDMA_INT0_LIST2_
NOTIFY_ENA_SET
VPDMA_INT0_LIST2_
COMPLETE_ENA_SE
T
VPDMA_INT0_LIST1_
NOTIFY_ENA_SET
VPDMA_INT0_LIST1_
COMPLETE_ENA_SE
T
VPDMA_INT0_LIST0_
NOTIFY_ENA_SET
VPDMA_INT0_LIST0_
COMPLETE_ENA_SE
T
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-174. intc_intr0_ena_set0 Register Field Descriptions
Bit Field Type Reset Description
31 SDVENC_INT_ENA_SET R/W 0h
SD_VENC Interrupt Enable/Set Read indicates interrupt enable 0 =
disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
30 DVO2_INT2_ENA_SET R/W 0h
DVO2 Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
29 DVO2_INT1_ENA_SET R/W 0h
DVO2 Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
28 DVO2_INT0_ENA_SET R/W 0h
DVO2 Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
27-25 Reserved R 0h
24 DVO1_INT2_ENA_SET R/W 0h
DVO1 Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
23 DVO1_INT1_ENA_SET R/W 0h
DVO1 Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
22 DVO1_INT0_ENA_SET R/W 0h
DVO1 Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
21 VIP2_PARSER_INT_ENA
_SET R/W 0h
VIP2 Parser Enable/Set Read indicates interrupt enable 0 = disabled
1 = enabled Writing 1 will set interrupt enabled Writing 0 has no
effect
20 VIP1_PARSER_INT_ENA
_SET R/W 0h
VIP1 Parser Enable/Set Read indicates interrupt enable 0 = disabled
1 = enabled Writing 1 will set interrupt enabled Writing 0 has no
effect
19 Reserved R 0h
18 DEI_FMD_INT_ENA_SET R/W 0h
DEI Film Mode Enable/Set Read indicates interrupt enable 0 =
disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
17 Reserved R 0h