Texas Instruments DM38x DaVinci, User Manual

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Registers
437 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.36 clkc_clken Register (offset = 100h) [reset = 0h]
clkc_clken is shown in Figure 1-292 and described in Table 1-203 .
Clock Enable Register
Figure 1-292. clkc_clken Register
31 30 29 28 27 26 25 24
Reserved NF_DP_EN
R-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved VIP2_DP_EN VIP1_DP_EN
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved SDVENC_EN DVO2_EN HDCOMP_EN HDMI_DVO1_EN IND_TRANS2_DP_E
N
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
IND_TRANS1_DP_E
N
COMP_DP_EN GRPX3_DP_EN GRPX2_DP_EN GRPX1_DP_EN AUX_DP_EN PRIM_DP_EN VPDMA_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-203. clkc_clken Register Field Descriptions
Bit Field Type Reset Description
31-25 Reserved R 0h
24 NF_DP_EN R/W 0h
Noise Filter Data Path Clock Enable.. 1 = Clock Enabled.. 0 = Clock
Disabled
23-18 Reserved R 0h
17 VIP2_DP_EN R/W 0h
Video Input Port 2 Data Path Clock Enable.. 1 = Clock Enabled.. 0 =
Clock Disabled
16 VIP1_DP_EN R/W 0h
Video Input Port 1 Data Path Clock Enable.. 1 = Clock Enabled.. 0 =
Clock Disabled
15-13 Reserved R 0h
12 SDVENC_EN R/W 0h
SD VENC Clock Enable.. 1 = Clock Enabled.. 0 = Clock Disabled
11 DVO2_EN R/W 0h
DVO2 VENC Clock Enable.. 1 = Clock Enabled.. 0 = Clock Disabled
10 HDCOMP_EN R/W 0h HDCOMP VENC Clock Enable.. 1 = Clock Enabled.. 0 = Clock
Disabled
9 HDMI_DVO1_EN R/W 0h
HDMI/DVO1 VENC Clock Enable.. 1 = Clock Enabled.. 0 = Clock
Disabled
8 IND_TRANS2_DP_EN R/W 0h
Independent Transcode 2 (to VIP1) Data Path Clock .. 1 = Clock
Enabled.. 0 = Clock Disabled
7 IND_TRANS1_DP_EN R/W 0h
Independent Transcode 1 (to VIP2) Data Path Clock .. 1 = Clock
Enabled.. 0 = Clock Disabled
6 COMP_DP_EN R/W 0h
Compositor Data Path Clock Enable.. 1 = Clock Enabled.. 0 = Clock
Disabled
5 GRPX3_DP_EN R/W 0h
Graphics 3 Data Path Clock Enable.. 1 = Clock Enabled.. 0 = Clock
Disabled
4 GRPX2_DP_EN R/W 0h
Graphics 2 Data Path Clock Enable.. 1 = Clock Enabled.. 0 = Clock
Disabled
3 GRPX1_DP_EN R/W 0h
Graphics 1 Data Path Clock Enable.. 1 = Clock Enabled.. 0 = Clock
Disabled
2 AUX_DP_EN R/W 0h
Auxiliary Video Data Path Clock Enable.. 1 = Clock Enabled.. 0 =
Clock Disabled