Texas Instruments DM38x DaVinci, User Manual

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Registers
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382 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.8 intc_intr0_ena_set1 Register (offset = 34h) [reset = 0h]
intc_intr0_ena_set1 is shown in Figure 1-264 and described in Table 1-175 .
Interrupt0 Enable/Set Register 1
Figure 1-264. intc_intr0_ena_set1 Register
31 30 29 28 27 26 25 24
Reserved VIP2_CHR_DS_2_UV
_ERR_INT_ENA_SET VIP2_CHR_DS_1_UV
_ERR_INT_ENA_SET
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
VIP1_CHR_DS_2_UV
_ERR_INT_ENA_SET VIP1_CHR_DS_1_UV
_ERR_INT_ENA_SET NF_CHR_DS_UV_ER
R_INT_ENA_SET
COMP_ERR_INT_EN
A_SET
GRPX3_INT_ENA_SE
T
GRPX2_INT_ENA_SE
T
GRPX1_INT_ENA_SE
T
DEI_ERROR_INT_EN
A_SET
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
VPDMA_INT0_CLIEN
T_ENA_SET
VPDMA_INT0_CHAN
NEL_GROUP6_ENA_
SET
VPDMA_INT0_CHAN
NEL_GROUP5_ENA_
SET
VPDMA_INT0_CHAN
NEL_GROUP4_ENA_
SET
VPDMA_INT0_CHAN
NEL_GROUP3_ENA_
SET
VPDMA_INT0_CHAN
NEL_GROUP2_ENA_
SET
VPDMA_INT0_CHAN
NEL_GROUP1_ENA_
SET
VPDMA_INT0_CHAN
NEL_GROUP0_ENA_
SET
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-175. intc_intr0_ena_set1 Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R 0h
25 VIP2_CHR_DS_2_UV_ER
R_INT_ENA_SET R/W 0h
VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates
interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt
enabled Writing 0 has no effect
24 VIP2_CHR_DS_1_UV_ER
R_INT_ENA_SET R/W 0h
VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates
interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt
enabled Writing 0 has no effect
23 VIP1_CHR_DS_2_UV_ER
R_INT_ENA_SET R/W 0h
VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates
interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt
enabled Writing 0 has no effect
22 VIP1_CHR_DS_1_UV_ER
R_INT_ENA_SET R/W 0h
VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates
interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt
enabled Writing 0 has no effect
21 NF_CHR_DS_UV_ERR_I
NT_ENA_SET R/W 0h
Noise Filter Chroma Downsampler UV error Interrupt Enable/Set
Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1
will set interrupt enabled Writing 0 has no effect
20 COMP_ERR_INT_ENA_S
ET R/W 0h
COMP Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
19 GRPX3_INT_ENA_SET R/W 0h
GRPX3 Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
18 GRPX2_INT_ENA_SET R/W 0h
GRPX2 Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
17 GRPX1_INT_ENA_SET R/W 0h
GRPX1 Enable/Set Read indicates interrupt enable 0 = disabled 1 =
enabled Writing 1 will set interrupt enabled Writing 0 has no effect
16 DEI_ERROR_INT_ENA_S
ET R/W 0h
DEI Error Enable/Set Read indicates interrupt enable 0 = disabled 1
= enabled Writing 1 will set interrupt enabled Writing 0 has no effect
15-8 Reserved R 0h
7 VPDMA_INT0_CLIENT_E
NA_SET R/W 0h
VPDMA INT0 Client Enable/Set Read indicates interrupt enable 0 =
disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect