Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 184 / 308

184 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Section E: Registers
Register Map Bank 0 Table: User Space
Na
m
e
Ad
dr
(0,
H
ex)
Acces
s
Pa
ge
Na
m
e
Ad
dr
(0,
H
ex)
Acces
s
Pa
ge
Na
m
e
Ad
dr
(0,
H
ex)
Acces
s
Pa
ge
Na
m
e
Ad
dr
(0,
H
ex)
Acces
s
Pa
ge
PRT0DR 00 RW 188 EP1_CNT0 40 # 201 80 C0
PRT0IE 01 RW 189 EP1_CNT1 41 RW 202 81 C1
02 EP2_CNT0 42 # 201 82 C2
03 EP2_CNT1 43 RW 202 83 C3
PRT1DR 04 RW 188 EP3_CNT0 44 # 201 84 C4
PRT1IE 05 RW 189 EP3_CNT1 45 RW 202 85 C5
06 EP4_CNT0 46 # 201 86 C6
07 EP4_CNT1 47 RW 202 87 C7
PRT2DR 08 RW 188 EP5_CNT0 48 # 201 88 I2C_XCFG C8 RW 226
PRT2IE 09 RW 189 EP5_CNT1 49 RW 202 89 I2C_XSTAT C9 R 227
0A EP6_CNT0 4A # 201 8A I2C_ADDR CA RW 228
0B EP6_CNT1 4B RW 202 8B I2C_BP CB R 229
PRT3DR 0C RW 188 EP7_CNT0 4C # 201 8C I2C_CP CC R 230
PRT3IE 0D RW 189 EP7_CNT1 4D RW 202 8D CPU_BP CD RW 231
0E EP8_CNT0 4E # 201 8E CPU_CP CE R 232
0F EP8_CNT1 4F RW 202 8F I2C_BUF CF RW 233
PRT4DR 10 RW 188 50 90 CUR_PP D0 RW 234
PRT4IE 11 RW 189 51 91 STK_PP D1 RW 235
12 52 92 D2
13 53 93 IDX_PP D3 RW 236
14 54 94 MVR_PP D4 RW 237
15 55 95 MVW_PP D5 RW 238
16 56 96 I2C_CFG D6 RW 239
17 57 97 I2C_SCR D7 # 240
18 PMA0_DR 58 RW 203 98 I2C_DR D8 RW 241
19 PMA1_DR 59 RW 203 99 D9
1A PMA2_DR 5A RW 203 9A INT_CLR0 DA RW 242
1B PMA_DR 5B RW 203 9B INT_CLR1 DB RW 244
1C PMA4_DR 5C RW 203 9C INT_CLR2 DC RW 246
1D PMA5_DR 5D RW 203 9D DD
1E PMA6_DR 5E RW 203 9E INT_MSK2 DE RW 248
1F PMA7_DR 5F RW 203 9F INT_MSK1 DF RW 249
20 60 CS_CR0 A0 RW 211 INT_MSK0 E0 RW 250
21 AMUX_CFG 61 RW 204 CS_CR1 A1 RW 212 INT_SW_EN E1 RW 251
22 62 CS_CR2 A2 RW 213 INT_VC E2 RC 252
23 63 CS_CR3 A3 RW 214 RES_WDT E3 W 253
24 PMA8_DR 64 RW 203 CS_CNTL A4 RW 215 E4
25 PMA9_DR 65 RW 203 CS_CNTH A5 RW 216 E5
26 PMA10_DR 66 RW 203 CS_STAT A6 # 217 E6
27 PMA11_DR 67 RW 203 CS_TIMER A7 RW 218 E7
28 PMA12_DR 68 RW 203 CS_SLEW A8 RW 219 E8
SPI_TXR 29 W 190 PMA13_DR 69 RW 203 PRS_CR A9 RW 220 E9
SPI_RXR 2A R 191 PMA14_DR 6A RW 203 AA EA
SPI_CR 2B # 192 PMA15_DR 6B RW 203 AB EB
2C TMP_DR0 6C RW 266 AC EC
2D TMP_DR1 6D RW 266 AD ED
2E TMP_DR2 6E RW 266 AE EE
2F TMP_DR3 6F RW 266 AF EF
30 70 PT0_CFG B0 RW 221 F0
USB_SOF0 31 R 193 71 PT0_DATA1 B1 RW 223 F1
USB_SOF1 32 R 194 72 PT0_DATA0 B2 RW 223 F2
USB_CR0 33 RW 195 73 PT1_CFG B3 RW 224 F3
USBIO_CR0 34 # 196 74 PT1_DATA1 B4 RW 223 F4
USBIO_CR1 35 # 197 75 PT1_DATA0 B5 RW 223 F5
EP0_CR 36 # 198 76 PT2_CFG B6 RW 225 F6
EP0_CNT0 37 # 199 77 PT2_DATA1 B7 RW 223 CPU_F F7 RL 254
EP0_DR0 38 RW 200 CMP_RDC 78 # 205 PT2_DATA0 B8 RW 223 F8
EP0_DR1 39 RW 200 CMP_MUX 79 RW 206 B9 F9
EP0_DR2 3A RW 200 CMP_CR0 7A RW 207 BA FA
EP0_DR3 3B RW 200 CMP_CR1 7B RW 208 BB FB
EP0_DR4 3C RW 200 CMP_LUT 7C RW 210 BC FC
EP0_DR5 3D RW 200 7D BD IDAC_D FD RW 256
EP0_DR6 3E RW 200 7E BE CPU_SCR1 FE # 257
EP0_DR7 3F RW 200 7F BF CPU_SCR0 FF # 258
Gray fields are reserved. # Access is bit specific.
[+] Feedback