Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 153 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 153
SPI
Normal Operation. Typical timing for an SPIM transfer is
shown in Figure 18-5 and Figure 18-6 . The user initially
writes a byte to transmit when TX Reg Empty status is true.
If no transmission is currently in progress, the data is loaded
into the shifter and the transmission is initiated. The TX Reg
Empty status is asserted again and the user is allowed to
write the next byte to be transmitted to the TX Buffer regis-
ter.
After the last bit is output, if TX Buffer data is available with
one-half clock setup time to the next clock, a new byte trans-
mission is initiated. An SPIM block receives a byte at the
same time that it sends one. The SPI Complete or RX Reg
Full can be used to determine when the input byte has been
received.
Figure 18-5. Typical SPIM Timing in Mode 0 and 1
INTERNAL CLOCK
TX REG EMPTY
D7 MOSI D6 D5 D2 D1 D0 D7
User writes first
byte to the TX
Buffer register.
Shifter is loaded
with first byte.
User writes next
byte to the TX
Buffer register.
SCLK (MODE 0)
Shifter is loaded
with next byte.
Last bit of received
data is valid on this
edge and is latched
into RX Buffer.
CLK INPUT
Free running,
internal bit rate
clock is CLK input
divided by two.
Setup time
for TX
Buffer write.
SCLK (MODE 1)
RX REG FULL
First input bit
is latched.
First shift.
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