Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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208 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
CMP_CR1
0,7Bh
21.3.21 CMP_CR1
Comparator Control Register 1
This register is used to configure the comparator output options.
For additional information, refer to the Register Definitions on page 103 in the Comparators chapter .
7 CINT1 This bit selects comparator 1 for input to the analog interrupt. Note that if both CINT1 and CINT0 are
set high, a rising edge on either comparator output may cause an interrupt.
0
Comparator 1 does not connect to the analog interrupt.
1 Comparator 1 connects to the analog interrupt. A rising edge asserts that interrupt, if it is
enabled in the INT_MSK0 register.
6 CPIN1 This bit selects the comparator 1 signal for possible connection to the GPIO pin. Connection to the
pin also depends on the configuration of the OUT_P1 register.
0
Select comparator 1 LUT output.
1 Select comparator 1 Latch output.
5 CRST1 This bit selects the source for resetting the comparator 1 latch.
0
Reset by writing a ‘0’ to the CMP_RDC register’s CMP1L bit.
1 Reset by rising edge of comparator 0 LUT output.
4 CDS1 This bit selects the data output for the comparator 1 channel, for routing to the capacitive sense logic
and comparator 1 interrupt.
0
Select the comparator 1 LUT output.
1 Select the comparator 1 latch output.
3 CINT0 This bit selects comparator 0 for input to the analog interrupt. Note that if both CINT1 and CINT0 are
set high, a rising edge on either comparator output may cause an interrupt.
0
Comparator 0 does not connect to the analog interrupt.
1 Comparator 0 connects to the analog interrupt. A rising edge asserts that interrupt, if it is
enabled in the INT_MSK0 register.
2 CPIN0 This bit selects the comparator 0 signal for possible connection to the GPIO pin. Connection to the
pin also depends on the configuration of the OUT_P1 register.
0
Select comparator 0 LUT output.
1 Select comparator 0 Latch output.
1 CRST0 This bit selects the source for resetting the comparator 0 latch.
0
Reset by writing a ‘0’ to the CMP_RDC register’s CMP0L bit.
1 Reset by rising edge of comparator 1 LUT output.
(continued on next page)
Individual Register Names and Addresses:
0,7Bh
CMP_CR1 : 0,7Bh
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0
Bit Name CINT1 CPIN1 CRST1 CDS1 CINT0 CPIN0 CRST0 CDS0
Bit Name Description
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