PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
239
I2C_CFG
0,D6h
21.3.51 I2C_CFG
I
2
C Configuration Register
This register is used to set the basic operating modes, baud rate, and interrupt selection.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the
Register Definitions on page 122
in the
I2C Slave chapter
.
6
P Select
I2C Pin Select.
0
P1[5] and P1[7].
1
P1[0] and P1[1].
Note
Read the I2C Slave chapter for a discussion of the side effects of choosing the P1[0] and P1[1]
pair of pins.
4
Stop IE
Stop Interrupt Enable.
0
Disabled.
1
Enabled. An interrupt is generated on the detection of a Stop condition.
3:2
Clock Rate[1:0]
00b
100K Standard Mode.
01b
400K Fast Mode.
10b
50K Standard Mode.
11b
Reserved..
0
Enable
0
Disabled.
1
Enabled.
Individual Register Names and Addresses:
0,D6h
I2C_CFG : 0,D6h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
PSelect
Stop IE
Clock Rate[1:0]
Enable
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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