60
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
General Purpose I/O (GPIO)
6.2.3
PRTxDMx Registers
The Port Drive Mode Bit Registers (PRTxDM0 and
PRTxDM1) specify the Drive mode for GPIO pins.
Bits 7 to 0: Drive Mode x[7:0].
In the PRTxDMx registers
there are four possible drive modes for each port pin. Two
mode bits are required to select one of these modes, and
these two bits are spread into two different registers
(PRTxDM0 and PRTxDM1). The bit position of the affected
port pin (for example, Pin[2] in Port 0) is the same as the bit
position of each of the two drive mode register bits that con-
trol the Drive mode for that pin (for example, bit[2] in
PRT0DM0 and bit[2] in PRT0DM1). The two bits from the
two registers are treated as a group. These are referred to
as DM1 and DM0, or together as DM[1:0]. Drive modes are
shown in
.
For analog I/O, set the drive mode to the High Z analog
mode, 10b. The 10b mode disables the block’s digital input
buffer so no crowbar current flows, even when the analog
input is not close to either power rail. If the 10b drive mode is
used, the pin is always read as a zero by the CPU and the
pin cannot generate a useful interrupt. (It is not strictly
required that you select High Z mode for analog operation.)
When digital inputs are needed on the same pin as analog
inputs, use the 11b Drive mode with the corresponding data
bit (in the PRTxDR register) set high.
The GPIO provides a default drive mode of high impedance,
analog (High Z). This is achieved by forcing the reset state
of all PRTxDM1 registers to FFh.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,xxh
Drive Mode 0[7:0]
RW : 00
1,xxh
Drive Mode 1[7:0]
RW :
FF
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
refer to the
Core Register Summary on page 24
Drive
Modes
Pin State
Description
DM1
DM0
0
0
Resistive pull up
Resistive high, strong low
0
1
Strong drive
Strong high, strong low
1
0
High impedance,
analog (
reset state
)
High Z high and low, digital input dis-
abled (for zero power) (
reset state
)
1
1
Open drain low
High Z high (digital input enabled),
strong low.
Summary of Contents for PSoC CY8CTMG20 Series
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