Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 212 / 308

212 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
CS_CR1
0,A1h
21.3.24 CS_CR1
TrueTouch Control Register 1
This register contains additional TrueTouch system control options.
Never write to this register while the block is enabled. For additional information, refer to the Register Definitions on page 92
in the TrueTouch Module chapter
.
7 CHAIN Counter chain control.
0
8-bit high/low counters operate independently.
1 High/low counters operate as a 16-bit synchronous block.
6:5 CLKSEL[1:0] TrueTouch clock (CSCLK) selection.
00b
IMO.
01b IMO/2.
10b IMO/4.
11b IMO/8.
4 RLOCLK Relaxation oscillator clock (RLO) select.
0
High byte counter runs on the selected IMO-based frequency.
1 High byte counter runs on the RLO clock frequency.
3 INV Input invert.
0
Selected input is not inverted.
1 Selected input is inverted.
2:0 INSEL[2:0] Input selection.
000b
Comparator 0.
001b ILO.
010b Comparator 1.
011b RLO Timer Terminal Count.
100b Interval Timer.
101b RLO Timer IRQ.
110b Analog Global Mux Bus.
111b ‘0’.
Individual Register Names and Addresses:
0,A1h
CS_CR1 : 0,A1h
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0
Bit Name CHAIN CLKSEL[1:0] RLOCLK INV INSEL[2:0]
Bit Name Description
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