Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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204 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
AMUX_CFG
0,61h
21.3.17 AMUX_CFG
Analog Mux Configuration Register
This register is used to configure the integration capacitor pin connections to the analog global bus.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on
page 100 in the I/O Analog Mux chapter.
5 PRX_MODE When this bit is set to 1, CS_CLK from TrueTouch counter logic block toggles regardless of the "EN"
bit setting in CS_CR0 register. When this bit is 0 CS_CLK is gated by "EN" bit in CS_CR0 register.
This bit is typically used in Proximity detection mode.
3:2 ICAPEN[1:0] Bits connect internal capacitance to the analog global bus.
00b
No capacitance
01b Approximately 25 pF connected
10b Approximately 50 pF connected
11b Approximately 100 pF connected
1:0 INTCAP[1:0] Select pins to enable connection of external integration capacitor in the charge integration mode.
00b
Neither P0[3] or P0[1] enabled
01b P0[1] pin enabled
10b P0[3] pin enabled
11b Both P0[3] and P0[1] pins enabled
Individual Register Names and Addresses:
0,61h
AMUX_CFG : 0,61h
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RW : 0
Bit Name PRX_MODE ICAPEN[1:0] INTCAP[1:0]
Bits Name Description
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