Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 132 / 308

132 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
I2C Slave
15.4.4 Slave Stall Timing
When a byte complete interrupt occurs, the PSoC device firmware must respond with a write to the I2C_SCR Register to con-
tinue the transfer (or terminate the transfer). The interrupt occurs two clocks after the rising edge of SCL_IN (see Status Tim-
ing on page 131 ). As illustrated in Figure 15-11 , firmware has until one clock after the falling edge of SCL_IN to write to the
I2C_SCR Register ; otherwise, a stall occurs. After stalled, the I/O write releases the stall. The setup time between data output
and the next rising edge of SCL is always N-1 clocks.
Figure 15-11. Slave Stall Timing
15.4.5 Implementation
The I2C block responds to transactions during sleep if and
only if:
a. The I2C slave block is enabled, i.e., bit 0 of the
I2C_CFG Register is set to 1'b1.
b. If I2C_ON is set or the USB Enable bit of USB_CR0
is set.
c. PD signal from the sleep controller is high.
To enable the wakeup through I2C, set the HW Addr EN bit
so that the I2C slave block wakes the system if and only if
the address matches.
Figure 15-12 depicts the wakeup
sequence through I2C.
Note The last step in this flowchart where SCL is released in
general, represents the configuration where buffer mode is
enabled.
Figure 15-12. I2C Wakeup Sequence
SCL
CLOCK
SCL_IN
(Synchronized)
SDA_OUT
I/O WRITE
1 Clocks N-1 Clocks
STALL No STALL
SCL_OUT
I2C Sleep
Enabled?
Start
Detect
Device Address
Matched?
Wakeup system by interrupt
and pull the SCL low
ACK the address byte and
release the SCL line once
IMO is operational
Send NACK
No
Yes
Yes
No
Yes
No
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