PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
275
IO_CFG2
1,DEh
21.4.16 IO_CFG2
Input/Output Configuration Register 2
The Input/Output Configuration 2 Register (IO_CFG2) selects output regulated supply and clock rates.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved
bits should always be written with a value of ‘0’. For additional information, refer to the
GPIO chapter.
5:3
REG_LEVEL[2:0]
These bits select output regulated supply
1:0
REG_CLOCK[1:0]
The Regulated I/O charge pump can operate with a maximum clock speed of 12 MHZ. The
REG_CLOCK[1:0] bits select clocking options for the regulator. Setting REG_CLOCK[1:0] to ‘10’
should be used with 24 MHz SYSCLK and ‘01’ should be used with 6/12 MHz SYSCLK.
Individual Register Names and Addresses:
1,DEh
IO_CFG2 : 1,DEh
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
Bit Name
REG_LEVEL[2:0]
REG_CLOCK[1:0]
Bits
Name
Description
REG_LEVEL[2:0]
Approx. Regulated Supply (V)
000
3
2.5
1.8
001
3.1
2.6
1.9
010
3.2
2.7
2.0
011
3.3
2.8
2.1
100
3.4
2.9
2.2
101
3.5
3.0
2.3
110
3.6
3.1
2.4
111
3.7
3.2
2.5
REG_CLOCK[1:0]
SYSCLK Clock Rate
10
24 MHz
01
6/12 MHz
Summary of Contents for PSoC CY8CTMG20 Series
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