Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 19 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 19
1. Pin Information
This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8CTMG20x, CY8CTMG20xA,
CY8CTST200, and CY8CTST200A PSoC devices. For up-to-date ordering, pinout, and packaging information, refer to the
individual PSoC device’s data sheet or go to
http://www.cypress.com .
1.1 Pinouts
The CY8CTMG20x, CY8CTMG20xA, CY8CTST200, and CY8CTST200A PSoC devices are available in a variety of pack-
ages. Every
port pin (labeled with a “P”), except for Vss , Vdd , and XRES in the following tables and illustrations, is capable
of Digital I/O.
1.1.1 CY8CTMG200-16LGXI, CY8CTMG200A-16LGXI, CY8CTST200-16LGXI,
CY8CTST200A-16LGXI PSoC 16-Pin Part Pinout
Table 1-1. 16-Pin QFN/COL Part Pinout
Pin
No.
Type
Name Description
CY8CTMG200-16LGXI, CY8CTMG200A-16LGXI,
CY8CTST200-16LGXI CY8CTST200A-16LGXI PSoC
Devices
Digital Analog
1 IO I P2[5] XTAL Out
2 IO I P2[3] XTAL In
3 IOHR I P1[7] I2C SCL, SPI SS
4 IOHR I P1[5] I2C SDA, SPI MISO
5 IOHR I P1[3] SPI CLK
6 IOHR I P1[1] TC CLK*, I2C SCL, SPI MOSI
7 Power Vss Ground pin
8 IOHR I P1[0] TC DATA*, I2C SDA, SPI CLK
9 IOHR I P1[2]
10 IOHR I P1[4] EXTCLK
11 Input XRES Active high external reset with internal pull down
12 IOH I P0[4]
13 Power Vdd Power pin
14 IOH I P0[7]
15 IOH I P0[3] Integrating input
16 IOH I P0[1] Integrating input
LEGEND
A = Analog, I = Input, O = Output, H = 5 mA High Output Drive, R = Regulated Output Option.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
P2[5]
P1[7]
P1[5]
P1
[3
]
P0
[3]
P0
[7]
Vd
d
P0[4]
P1
[1
]
P1
[0
]
P1[2]
P2[3]
P1[4]
XRES
P0
[1]
Vs
s
QFN
(Top View)
1
2
3
4
12
11
10
9
16 15 14
13
5 6 7 8
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