Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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46 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Interrupt Controller
4. Program execution vectors to the interrupt table. Typi-
cally an
LJMP
instruction in the interrupt table sends exe-
cution to the user's interrupt service routine for this
interrupt. (See
Instruction Set Summary on page 28 .)
5. The ISR executes. Interrupts are disabled since GIE = 0.
In the ISR, interrupts can be re-enabled if necessaty by
setting GIE = 1 (take care to avoid stack overflow in this
case).
6. The ISR ends with an RETI instruction. This pops the
Flag register, PCL, and PCH from the stack, restoring
those registers. The restored Flag register re-enables
interrupts since GIE = 1 again.
7. Execution resumes at the next instruction, after the
instruction that occurred before the interrupt. However, if
there are more pending interrupts, the subsequent inter-
rupts are processed before the next normal program
instruction.
Interrupt Latency. The time between the assertion of an
enabled interrupt and the start of its ISR is calculated using
this equation:
Latency =
Time for current instruction to
Time for M8C to change program counter to interrupt
a
Time for
LJMP
instruction in interrupt table to execute.
Equation 1
For example, if the 5-cycle
JMP
instruction is executing
when an interrupt becomes active, the total number of CPU
clock cycles before the ISR begins is:
Equation 2
In this example, at 24 MHz, 25 clock cycles take 1.042
μ
s.
Interrupt Priority. Interrupt priorities come into consider-
ation when more than one interrupt is pending during the
same instruction cycle. In this case, the Priority Encoder
(see
Figure 5-1 ) generates an interrupt vector for the highest
priority pending interrupt.
5.1.1 Posted versus Pending Interrupts
An interrupt is posted when its interrupt conditions occur.
This results in the flip-flop in
Figure 5-1 clocking in a 1. The
interrupt remains posted until the interrupt is taken or until it
is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by set-
ting its interrupt mask bit (in the appropriate INT_MSKx reg-
ister). All pending interrupts are processed by the Priority
Encoder to determine the highest priority interrupt taken by
the M8C if the Global Interrupt Enable bit is set in the
CPU_F register.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor
does it prevent an interrupt from posting. It simply prevents a
posted interrupt from becoming pending.
It is especially important to understand the functionality of
clearing posted interrupts, if the configuration of the PSoC
device is changed by the application.
For example, if a block has a posted interrupt when it is
enabled and then disabled, the posted interrupt remains.
Therefore, it is good practice to use the INT_CLR register to
clear posted interrupts before enabling or re-enabling a
block.
5.2 Application Overview
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in PSoC devices. Interrupts for all the digital
blocks and each of the analog columns are available, as well
as interrupts for supply voltage, sleep, variable clocks, and a
general GPIO (pin) interrupt.
The registers associated with the interrupt controller allow
for the disabling of interrupts either globally or individually.
The registers also provide a mechanism by which a user can
clear all pending and posted interrupts or clear individual
posted or pending interrupts. A software mechanism is pro-
vided to set individual interrupts. Setting an interrupt by way
of software is very useful during code development, when
one may not have the complete hardware system necessary
to generate a real interrupt.
Latency =
Time for current instruction to
Time for M8C to change program counter to interrupt a
Time for LJMP instruction in interrupt table to execute.
(1 to 5 cycles for JMP to finish) +
(13 cycles for interrupt routine) +
(7 cycles for LJMP) = 21 to 25 cycles.
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