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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
EP0_CR
0,36h
21.3.11 EP0_CR
Endpoint 0 Control Register
This register is an endpoint 0 control register.
For additional information, refer to the
Register Definitions on page 171
in the Full-Speed USB chapter.
7
Setup Received
When set, this bit indicates a valid setup packet was received and ACK’ed.
6
IN Received
When set, this bit indicates a valid IN packet was received.
5
OUT Received
When set, this bit indicates an OUT packet was received.
4
ACK’ed Transaction
When set, this bit indicates a valid OUT packet has been received and ACK’ed.
3:0
Mode[3:0]
The mode bits control how the USB SIE responds to traffic and how the USB SIE changes the mode
of that endpoint as a result of host packets to the endpoint.
Individual Register Names and Addresses:
0,36h
EP0_CR : 0,36h
7
6
5
4
3
2
1
0
Access : POR
RC : 0
RC : 0
RC : 0
RC : 0
RW : 0
Bit Name
Setup
Received
IN Received
OUT Received
ACK’ed
Transaction
Mode[3:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
