Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 96 / 308

96 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
TrueTouch Module
11.2.9 CS_SLEW Register
The TrueTouch Slew Control Register (CS_SLEW) enables
and controls a fast slewing mode for the relaxation oscillator.
Bits 7 to 1: FastSlew[6:0]. This 7-bit count sets the time
interval, in IMO cycles, for a faster slew rate on the relax-
ation oscillator edges. The interval applies to both rising and
falling edges. This timer value has no effect unless the
FS_EN bit is set high.
Bit 0: FS_EN. This bit enables the fast slewing interval on
each edge of the relaxation oscillator.
For additional information, refer to the CS_SLEW register on
page 219 .
11.2.10 PRS_CR Register
Pseudo Random Sequence and Prescaler Control Register
controls the prescaler and Pseudo Random Sequence gen-
erator output.
Bit 7: CS_CLK_OUT. This bit selects the TrueTouch clock
(inversion or non-inversion depending on bit 6 setting) to be
routed onto primary pin depending on the OUT_P1/OUT_P0
register selection.
Use a '1' to route prescaler output or PRS output (depending
on the CSD_PRSCLK in CS_CR0 when in CSD mode) or
route the clock based on CLKSEL bits in the CS_CR1 regis-
ter in normal TrueTouch mode to primary pins P1[2]/P0[7]
(depending on OUT_P1/OUT_P0 bit selections instead of
the normal CSOUT[1:0] selections). See the OUT_P1/
OUT_P0 registers for more details. Use a '0' to use CSOUT
[1:0] selections as normal.
Bit 6: CS_CLK_INV. This bit allows you to selectively route
either the TrueTouch clock or the inversion of the TrueTouch
clock onto a pin. A '1' routes inverted TrueTouch clock to pin
(see bit 7). A '0' routes non-inverted TrueTouch clock to pin
(see bit 7).
Bit 5: PRS_12BIT. This bit allows selection between 8-bit
PRS or 12-bit PRS output. With '0', the MSB of the 8-bit PRS
is sent out. With '1', the MSB of the 12-bit PRS is sent out.
Bit 4: PRS_EN. This bit is used to enable or disable the
PRS block. With '0', the PRS is disabled. The PRS block
output is 0. With '1', the PRS is enabled and bit 5 decides
whether the MSB of the 12-bit PRS is sent out or the MSB of
the 8-bit PRS is sent out.
Bit 3: PRESCALE_BYP. This bit is used to bypass the
prescaler and pass the input clock undivided onto the out-
put. The output of the prescaler feeds the clock input to the
PRS block. With '0', the divided clock is sent out of the pres-
caler depending on the setting of bit [2:0]. With '1', the
incoming IMO clock is sent out of the prescaler without any
division.
Bits 2 to 0: PRESCALE_CLK_DIV[2:0]. These bits allow
the selection of one of eight frequencies of the incoming
IMO clock to be fed as input to the PRS block.
For additional information, refer to the PRS_CR register on
page 220 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,A8h CS_SLEW FastSlew[6:0] FS_EN RW : 00
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,A9h PRS_CR CS_CLK_OUT CS_CLK_INV PRS_12BIT PRS_EN PRESCALE
_BYP
PRESCALE_CLK_DIV[2:0] RW : 00
PRESCALE_CLK_DIV[2:0] Description
000 Divides the input IMO clock by 2
001 Divides the input IMO clock by 4
010 Divides the input IMO clock by 8
011 Divides the input IMO clock by 16
100 Divides the input IMO clock by 32
101 Divides the input IMO clock by 64
110 Divides the input IMO clock by 128
111 Divides the input IMO clock by 256
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