Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 141 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 141
System Resets
16.4.4 Reset Details
Timing and functionality details are summarized in Table 16-1 . Figure 16-4 on page 140 shows some of the relevant signals
for IPOR, PPOR, XRES, and WDR.
16.5 Power Modes
The ILO block drives the CLK32K clock used to time most
events during the reset sequence. This clock is powered
down by IPOR but not by any other reset. The sleep timer
provides interval timing.
While POR or XRES assert, the IMO is powered off to
reduce startup power consumption.
During and following IRES (for 64 ms nominally), the IMO is
powered off for low average power during slow supply
ramps.
During and after POR or XRES, the bandgap circuit is pow-
ered up.
The IMO is always on for at least one CLK32K cycle before
CPU reset is deasserted.
Table 16-1. Reset Functionality
Item IPOR (Part of POR) PPOR (Part of POR) XRES WDR
Reset Length While POR=1
While PPOR=1, plus
30-60 µs (1-2 clocks)
While XRES=1 30 µs (1 clock)
Low Power (IMO Off) During Reset? Yes Yes Yes No
Low Power Wait Following Reset? No No No No
CLK32K Cycles from End of Reset to
CPU Reset Deasserts
a
a. CPU reset is released after synchronization with the CPU clock.
512 1
8
1
Register Reset
(See Next Line for CPU_SCR0,
CPU_SCR1)
All
All, except PPOR does not
reset Bandgap Trim
register
All All
Reset Status Bits in CPU_SCR0,
CPU_SCR1
Set PORS,
Clear WDRS,
Clear IRAMDIS
Set PORS,
Clear WDRS,
Clear IRAMDIS
Set PORS,
Clear WDRS,
Clear IRAMDIS
Clear PORS,
Set WDRS,
IRAMDIS unchanged
Bandgap Power On On On On
Boot Time
b
b. Measured from CPU reset release to execution of the code at Flash address 0x0000.
2.2 ms 2.2 ms 2.2 ms 2.2 ms
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