196
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
USBIO_CR0
0,34h
21.3.9
USBIO_CR0
USB I/O Control Register 0
This register is a USBIO manual control register 0.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
in the Full-Speed USB chapter.
7
TEN
Transmit Enable. This bit is used to manually transmit on D+, D- pins. Normally, this bit must be
cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting
is to force a resume state on the bus.
0
Manual transmission off.
1
Manual transmission enabled.
6
TSE0
Both D+ and D- are low. There is no effect if TEN=0.
5
TD
This bit transmits a USB J or K state on the USB bus. There is no effect if TEN=0 or TSE0=1.
0
Force USB K state.
1
Force USB J state.
0
RD
This read only bit gives the state of the USB differential receiver.
0
D+ < D- or D+ = D- = 0.
1
D+ > D-.
Individual Register Names and Addresses:
0,34h
USBIO_CR0 : 0,34h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
R : 0
Bit Name
TEN
TSE0
TD
RD
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
