Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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152 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SPI
18.3.2 SPIM Timing
Enable/Disable Operation. As soon as the block is config-
ured for SPIM, the primary output is the MSb or LSb of the
Shift register, depending on the LSb First configuration in bit
7 of the Control register. The auxiliary output is '1' or '0',
depending on the idle clock state of the SPI mode. This is
the idle state.
Clock Generation. Figure 18-4 illustrates the SPIM input
clocking scheme. The SYSCLK pin is an input into an eight-
stage ripple divider that provides the baud rate selections.
When the block is disabled, all internal state is held in a
reset state.
When the Enable bit in the SPI_CR register is set, the reset
is synchronously released and the clock generation is
enabled. All eight taps from the ripple divider are selectable
(/2, /4, /8, /16, /32, /64, /128, /256) from the Clock Sel bits in
the SPI_CFG register. The selected divider tap is resynchro-
nized to SYSCLK. The resulting clock is routed to all of the
synchronous elements in the design.
When the block is disabled, the SCLK and MOSI outputs
revert to their idle state. All internal state is reset (including
CR0 status) to its configuration-specific reset state, except
for DR0, DR1, and DR2, which are unaffected.
Figure 18-4. SPI Input Clocking
IO WRITE
SYSCLK
4
2
8
Two SYSCLKs to first block clock.
ENABLE
BLOCK RESET
RESYNC CLOCK
Default 2
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