Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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130 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
I2C Slave
15.4 Timing Diagrams
15.4.1 Clock Generation
Figure 15-6 illustrates the I
2
C input clocking scheme. The SYSCLK pin is an input into a three-stage ripple divider that pro-
vides the baud rate selections. When the block is disabled, all internal state is held in a reset state. When the Enable bit in the
I2C_CFG Register is set, the reset is synchronously released and the clock generation is enabled. All three taps from the rip-
ple divider are selectable (/2, /4, /8) from the clock rate bits in the I2C_CFG Register . If any of the three divider taps is
selected, that clock is resynchronized to SYSCLK. The resulting clock is routed to all of the synchronous elements in the
design.
Figure 15-6. I
2
C Input Clocking
15.4.2 Basic I/O Timing
Figure 15-7 illustrates basic input/output timing that is valid for both 16 times sampling and 32 times sampling. For 16 times
sampling, N=4; for 32 times sampling, N=12. N is derived from the half-bit rate sampling of eight and 16 clocks, respectively,
minus the input latency of three (count of 4 and 12 correspond to 5 and 13 clocks).
Figure 15-7. Basic Input/Output Timing
I/O WRITE
SYSCLK
4
2
8
Two SYSCLKS to first block clock.
ENABLE
BLOCK RESET
RESYNC CLOCK
Default
8
SCL
SCL_IN
CLOCK
SDA_OUT
CLK CTR N 1 2 N 0 1 2 N 0 0
SHIFT
SDA_IN
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