Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 136 / 308

136 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
System Resets
16.2.2 Powerup External Reset Behavior
The device’s core runs on chip regulated supply, so there is
a time delay in powering up the core. A short XRES pulse at
power up causes an external reset startup behavior. How-
ever, the event is latched and applied only after the core has
powered up (a delay of about 1 ms).
16.2.3 GPIO Behavior on External Reset
During External Reset (XRES=1), both P1[0] and P1[1] drive
resistive low (0). After XRES deasserts, these pins continue
to drive resistive low for another eight sleep clock cycles
(approximately 200
μ
s). After this time, both pins transition
to a high impedance state and normal CPU operation
begins. This is illustrated in
Figure 16-2 .
Figure 16-2. P1[1:0] Behavior on External Reset (XRES)
XRES
P1[0]
P1[1]
HiZ
HiZ
R0
R0
T1
T1 = 8 Sleep Clock Cycles
(approximately 200
μ
s)
[+] Feedback