Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 22 / 308

22 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Pin Information
1.1.4 CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, CY8CTST200-48LTXI,
CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC
48-Pin Part Pinout
Table 1-4. 48-Pin Part Pinout **
Pin
No.
Digit
a
l
Analog
Name Description
CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI,
CY8CTST200-48LTXI, CY8CTST200A-48LTXI,
CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC
Devices
1 NC No connection
2 IO I P2[7]
3 IO I P2[5] XTAL Out
4 IO I P2[3] XTAL In
5 IO I P2[1]
6 IO I P4[3]
7 IO I P4[1]
8 IO I P3[7]
9 IO I P3[5]
10 IO I P3[3]
11 IO I P3[1]
12 IOHR I P1[7] I2C SCL, SPI SS
13 IOHR I P1[5] I2C SDA, SPI MISO
14 NC No connection
15 NC No connection
16 IOHR I P1[3] SPI CLK
17 IOHR I P1[1] TC CLK*, I2C SCL, SPI MOSI
18 Power Vss Ground pin
19 IO D + USB PHY
20 IO D - USB PHY
21 Power Vdd Power pin
22 IOHR I P1[0] TC DATA*, I2C SDA, SPI CLK
23 IOHR I P1[2]
24 IOHR I P1[4] EXTCLK
25 IOHR I P1[6]
26 Input XRES Active high external reset with internal pull down
27 IO I P3[0]
28 IO I P3[2]
29 IO I P3[4]
30 IO I P3[6]
Pin
No.
Dig
it
a
l
Analog
Name Description 31 IO I P4[0]
32 IO I P4[2]
33 IO I P2[0] 41 Power Vdd Power pin
34 IO I P2[2] 42 NC No connection
35 IO I P2[4] 43 NC No connection
36 IO I P2[6] 44 IOH I P0[7]
37 IOH I P0[0] 45 IOH I P0[5]
38 IOH I P0[2] 46 IOH I P0[3] Integrating input
39 IOH I P0[4] 47 Power Vss Ground pin
40 IOH I P0[6] 48 IOH I P0[1] Integrating input
LEGEND
A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
* ISSP pin which is not High Z at POR (Power On Reset).
** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not
connected to ground, it must be electrically floated and not connected to any other signal.
QFN
(Top View)
P0
[1
]
Vs
s
P0
[3
]
P0
[5
]
P0
[7
]
NC NC Vd
d
P0
[6
]
P0
[4
]
P0
[2
]
P0
[0
]
10
11
12
P2[7]
NC
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48 47 46 45 44 43
42
41 40 39 38 37
P2[4]
P2[2]
P2[0]
P4[2]
P4[0]
P3[6]
P3[4]
P3[2]
P3[0]
XRES
P1[6]
P2[6]
1
2
3
4
5
6
7
8
9
13 14 15 16 17 18 19 20 21 22
23 24
P1
[5
]
NC NC
P1
[3
]
P1
[1
]
Vs
s
D+
D-
Vd
d
P1
[0
]
P1
[2
]
P1
[4
]
[+] Feedback