PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
65
Internal Main Oscillator (IMO)
7.3.3
CPU_SCR1 Register
The System Status and Control Register 1 (CPU_SCR1)
conveys the status and control of events related to internal
resets and watchdog reset.
Bit 7: IRESS.
The Internal Reset Status bit is a read only bit
that determines if the booting process occurred more than
once.
When this bit is set, it indicates that the SROM SWBootRe-
set code ran more than once. If this bit is not set, the
SWBootReset ran only once. In either case, the SWBootRe-
set code does not allow execution from code stored in Flash
until the M8C core is in a safe operating mode with respect
to supply voltage and Flash operation. There is no need for
concern when this bit is set. It is provided for systems that
may be sensitive to boot time, so that they can determine if
the normal one pass boot time was exceeded. For more
information on the SWBootReest code, see the
Supervisory
ROM (SROM) chapter on page 89
.
Bit 4 to 3: SLIMO[1:0].
These bits set the IMO frequency
range. See the table below for more information.
These changes allow for optimization of speed and power.
The IMO trim value must also be changed when SLIMO is
changed (see
). When not in
external clocking mode, the IMO is the source for SYSCLK;
therefore, when the speed of the IMO changes so does
SYSCLK.
Bit 0: IRAMDIS.
Initialize RAM Disable. This bit is a control
bit that is readable and writeable. The
for this
bit is ‘0’, which indicates that the maximum amount of SRAM
must be initialized upon watchdog reset to a value of 00h.
When the bit is ‘1’, the minimum amount of SRAM is initial-
ized after a watchdog reset.
For additional information, refer to the
7.3.4
OSC_CR2 Register
The Oscillator Control Register 2 (OSC_CR2) configures
various features of internal clock sources and clock nets.
Bit 4: CLK48MEN.
This is the 48 MHz clock enable bit. ‘0‘
disables the bit and ‘1‘ enables the bit. This register setting
applies only when the device is not in OCD mode. When in
OCD mode, the 48 MHz clock is always active.
Bit 2: EXTCLKEN.
When the EXTCLKEN bit is set, the
external clock becomes the source for the internal clock
tree, SYSCLK, which drives most device clocking functions.
All external and internal signals, including the low speed
oscillator, are synchronized to this clock source. The exter-
nal clock input is located on P1[4]. When using this input,
the pin drive mode must be set to High Z (not High Z ana-
log), such as drive mode 11b with PRT1DR bit 4 set high.
Bit 1: IMODIS.
When set, the Internal Main Oscillator (IMO)
is disabled.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
x,FEh
IRESS
SLIMO[1:0]
IRAMDIS
# : 0
LEGEND
x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used.
# Access is bit specific. Refer to the
Register Reference chapter on page 187
for additional information.
SLIMO
CY8CTMG20x, CY8CTST200
00
12
01
6
10
24
11
Reserved
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,E2h
CLK48MEN
EXTCLKEN
IMODIS
RW : 00
Summary of Contents for PSoC CY8CTMG20 Series
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Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
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Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
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