Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 119 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 119
I2C Slave
Figure 15-3. Slave Operation
15.2.2 EZI2C Mode
When EZI2C mode is configured with the Buffer Mode bit of
the I2C_XCFG register, both the master and slave must use
a predefined communication protocol. In this protocol, the
I
2
C slave operates as a RAM buffer interface, in which the
external master controls the read and write addresses to the
32-byte RAM buffer. The external master reads and writes
to the RAM buffer are independent of the CPU reads and
writes to the RAM buffer, so conceptually, it appears as a
dual port RAM buffer. Higher level protocols, such as polling
or semaphore methods, are used to ensure data synchroni-
zation and integrity. Conceptually, data is always available
in this mode so the bus never stalls except in I
2
C sleep
mode.
The RAM buffer interfaces contain separate address point-
ers, I2C_BP and I2C_CP, that are set with the first data byte
of a write operation. When the external master writes one or
more bytes, the first data byte is always the base address
pointer value. This value gets written to both the base
address pointer, I2C_BP, and the current address pointer,
I2C_CP. The byte after the base address pointer is written
into the location pointed to by the current address pointer
value contained in I2C_CP.
The third byte (second data byte) is written to the current
address pointer value, I2C_CP, plus one and so on. This
current address pointer, I2C_CP, increments for each byte
read or written, but is reset to the base address pointer
value at the beginning of each new write or read operation
(following a start command).
For example, if the base address pointer, I2C_BP, is set to
4, a read operation begins to read data at location 4 and
continues sequentially until the host completes the read
operation. So, if the base address pointer is set to 4, each
read operation resets the data pointer to 4 and reads
sequentially from that location. This is true whether single or
multiple read operations are performed. The base address
pointer is not changed until a new write operation initiates.
If the I
2
C master attempts to write data past the RAM
address boundary, 32 bytes, the data is discarded and does
not affect any RAM inside or outside the designated RAM
area. You cannot read data outside the allowed range. Any
read requests by the master outside the allowed range
result in the return of invalid data. If the RAM address is sent
1 7 8
1 7 8 9
STAR
T
7-Bit Address R/W
ACK
8-Bit Data
ACK/NACK
STOP
SHIFTER
M8C reads the received byte from
the I2C_DR register and checks for
“Own Address” and R/W.
1 7 8
8-Bit Data
STOP
SHIFTER
M8C writes the byte to transmit
to the I2C_DR register.
9
SHIFTER
Re
ad
(T
X)
W
rit
e
(R
X)
M8C writes (ACK) to
I2C_SCR register.
Slave Transmitter/Reciever
ACK/NACK
M8C issues ACK/NACK
command with a write to
the I2C_SCR register.
Master may
transmit another
byte or STOP.
M8C reads the received byte from
the I2C_DR register.
ACK = Master wants to
read another byte.
NACK = Master
says end-of-data.
NACK = Slave
says no more.
ACK = OK to
receive more.
A byte interrupt is generated.
The SCL line is held low.
An interrupt is generated on byte
complete. The SCL line is held low.
An interrupt is generated on a
complete byte + ACK/NACK.
The SCL line is held low.
ACK
M8C writes
(ACK | TRANSMIT) to
I2C_SCR register.
9
M8C writes a new byte to the I2C_DR
register and then writes a TRANSMIT
command to I2C_SCR to release the bus.
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