206
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
CMP_MUX
0,79h
21.3.19 CMP_MUX
Comparator Multiplexer Register
This register contains control bits for input selection of comparators 0 and 1.
For additional information, refer to the
Register Definitions on page 103
in the Comparators chapter
.
7:6
INP1[1:0]
Comparator 1 Positive Input Select
00b
Analog Global Mux Bus
01b
Reserved
10b
P0[1] pin
11b
P0[3] pin
5:4
INN1[1:0]
Comparator 1 Negative Input Select
00b
VREF (1.0V)
01b
Ref Lo (approximately 0.6V)
10b
Ref Hi (approximately 1.2V)
11b
Reserved
3:2
INP0[1:0]
Comparator 0 Positive Input Select
00b
Analog Global Mux Bus
01b
Reserved
10b
P0[1] pin
11b
P0[3] pin
1:0
INN0[1:0]
Comparator 0 Negative Input Select
00b
VREF (1.0V)
01b
Ref Lo (approximately 0.6V)
10b
Ref Hi (approximately 1.2V)
11b
Reserved
Individual Register Names and Addresses:
0,79h
CMP_MUX : 0,79h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
INP1[1:0]
INN1[1:0]
INP0[1:0]
INN0[1:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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