244
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
INT_CLR1
0,DBh
21.3.55 INT_CLR1
Interrupt Clear Register 1
This register is used to enable the individual interrupt sources' ability to clear posted interrupts.
When bits in this register are read, a '1' is returned for every bit position that has a corresponding posted interrupt. When bits
in this register are written with a '0' and ENSWINT is not set, posted interrupts are cleared at the corresponding bit positions.
If there is no posted interrupt, there is no effect. When bits in this register are written with a '1' and ENSWINT is set, an inter-
rupt is posted in the interrupt controller.
For additional information, refer to the
Register Definitions on page 48
in the Interrupt Controller chapter.
7
Endpoint3
Read 0 No posted interrupt for USB Endpoint3.
Read 1 Posted interrupt present for USB Endpoint3.
Write 0 AND ENSWINT = 0
Clear posted interrupt if it exists.
Write 1 AND ENSWINT = 0
No effect.
Write 0 AND ENSWINT = 1
No effect.
Write 1 AND ENSWINT = 1
Post an interrupt for USB Endpoint3.
6
Endpoint2
Read 0 No posted interrupt for USB Endpoint2.
Read 1 Posted interrupt present for USB Endpoint2.
Write 0 AND ENSWINT = 0
Clear posted interrupt if it exists.
Write 1 AND ENSWINT = 0
No effect.
Write 0 AND ENSWINT = 1
No effect.
Write 1 AND ENSWINT = 1
Post an interrupt for USB Endpoint2.
5
Endpoint1
Read 0 No posted interrupt for USB Endpoint1.
Read 1 Posted interrupt present for USB Endpoint1.
Write 0 AND ENSWINT = 0
Clear posted interrupt if it exists.
Write 1 AND ENSWINT = 0
No effect.
Write 0 AND ENSWINT = 1
No effect.
Write 1 AND ENSWINT = 1
Post an interrupt for USB Endpoint1.
(continued on next page)
Individual Register Names and Addresses:
0,DBh
INT_CLR1 : 0,DBh
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
Endpoint3
Endpoint2
Endpoint1
Endpoint0
USB_SOF
USB_BUS_RST
Timer2
Timer1
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
