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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Interrupt Controller
5.3
Register Definitions
The following registers are associated with the Interrupt Controller and are listed in address order. The register descriptions
have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are
reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0’. For a
complete table of Interrupt Controller registers, refer to the
Summary Table of the Core Registers on page 24
.
5.3.1
INT_CLR0 Register
The Interrupt Clear Register 0 (INT_CLR0) enables the indi-
vidual interrupt sources’ ability to clear posted interrupts.
The INT_CLR0 register is similar to the INT_MSK0 register
in that it holds a bit for each interrupt source. Functionally
the INT_CLR0 register is similar to the INT_VC register,
although its operation is completely independent. When the
INT_CLR0 register is read, any bits that are set indicate an
interrupt was posted for that hardware resource. Reading
this register gives the user the ability to determine all posted
interrupts.
The Enable Software Interrupt (ENSWINT) bit in the
INT_SW_EN register determines how an individual bit
value, written to an INT_CLR0 register, is interpreted. When
ENSWINT is cleared (the default state), writing 1's to the
INT_CLR0 register has no effect. However, writing 0's to the
INT_CLR0 register, when ENSWINT is cleared, causes the
corresponding interrupt to clear. If the ENSWINT bit is set,
any 0's written to the INT_CLR0 register are ignored. How-
ever, 1's written to the INT_CLR0 register, while ENSWINT
is set, cause an interrupt to post for the corresponding inter-
rupt.
Software interrupts aid in debugging interrupt service rou-
tines by eliminating the need to create system level interac-
tions that are sometimes necessary to create a hardware-
only interrupt.
Bit 7: I2C.
This bit allows posted I2C interrupts to be read,
cleared, or set.
Bit 6: Sleep.
This bit allows posted sleep interrupts to be
read, cleared, or set.
Bit 5: SPI.
This bit allows posted SPI interrupts to be read,
cleared, or set.
Bit 4: GPIO.
This bit allows posted GPIO interrupts to be
read, cleared, or set.
Bit 3: Timer0.
This bit allows posted timer interrupts to be
read, cleared, or set.
Bit 2: TrueTouch.
This bit allows posted TrueTouch inter-
rupts to be read, cleared, or set.
Bit 1: Analog.
This bit allows posted analog interrupts to
be read, cleared, or set.
Bit 0: V Monitor.
This bit allows posted voltage monitor
interrupts to be read, cleared, or set.
For additional information, refer to the
.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,DAh
I2C
Sleep
SPI
GPIO
Timer0
TrueTouch
Analog
V Monitor
RW : 00
Summary of Contents for PSoC CY8CTMG20 Series
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