Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 27
2. CPU Core (M8C)
This chapter explains the CPU Core, called the M8C, and its associated register. It covers the internal M8C registers, address
spaces,
instruction set and formats. For additional information concerning the M8C instruction set, refer to the PSoC
Designer Assembly Language User Guide available at the Cypress web site ( http://www.cypress.com ). For a quick reference
of all PSoC registers in address order, refer to the Register Reference chapter on page 187 .
2.1 Overview
The M8C is a four MIPS 8-bit Harvard architecture micropro-
cessor. Selectable processor clock speeds up to 24 MHz
enable you to tune the M8C to a particular application’s per-
formance and power requirements. The M8C supports a rich
instruction set that allows for efficient low-level language
support.
2.2 Internal Registers
The M8C has five internal registers that are used in program
execution. Here is a list of these registers.
■
Accumulator (A)
■
Index (X)
■
Program Counter (PC)
■
Stack Pointer (SP)
■
Flags (F)
All the internal M8C registers are 8 bits in width, except for
the PC which is 16 bits wide. Upon
reset , A, X, PC, and SP
are reset to 00h. The Flag register (F) is reset to 02h, indi-
cating that the Z
flag is set .
With each stack operation, the SP is automatically incre-
mented or decremented so that it always points to the next
stack
byte in RAM. If the last byte in the stack is at address
FFh
,
the stack pointer wraps to RAM address 00h. It is the
firmware developer’s responsibility to ensure that the stack
does not overlap with user defined variables in RAM.
With the exception of the F register, the M8C internal regis-
ters are not accessible via an explicit register address. The
internal M8C registers are accessed using these instruc-
tions:
■
MOV A, expr
■
MOV X, expr
■
SWAP A, SP
■
OR F, expr
■
JMP LABEL
The F register is read by using address F7h in either register
bank.
2.3 Address Spaces
The M8C has three address spaces: ROM , RAM , and regis-
ters. The ROM address space includes the Supervisory
ROM (SROM) and the Flash. The ROM address space is
accessed through its own address and
data bus .
The ROM address space is composed of the Supervisory
ROM and the on-chip Flash program store. Flash is orga-
nized into 128-byte blocks. Program store page boundaries
are not an issue because the M8C automatically increments
the 16-bit PC on every instruction. This makes the block
boundaries invisible to user code. Instructions occurring on
a 128-byte Flash page boundary (with the exception of
JMP
instructions) incur an extra M8C clock cycle, since the upper
byte of the PC is incremented.
The register address space is used to configure the PSoC
microcontroller’s programmable blocks. It consists of two
banks of 256 bytes each. To switch between banks, the XIO
bit in the Flag register is set or cleared (set for Bank1,
cleared for Bank0). The common convention is to leave the
bank set to Bank0 (XIO cleared), switch to Bank1 as needed
(set XIO), then switch back to Bank0.
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