Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 282 / 308

282 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
ILO_TR
1,E9h
21.4.23 ILO_TR
Internal Low Speed Oscillator Trim Register
This register sets the adjustment for the Internal Low Speed Oscillator (ILO).
It is strongly recommended that you do not alter this register’s Freq Trim[3:0] values. The trim bits are set to factory
specifications and must not be changed.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the
Register Definitions on page 68 in the
Internal Low Speed Oscillator chapter.
6 PD_MODE This bit selects power down mode. Setting this bit high disables oscillator and current bias, which
results in slower startup time.
Power down mode:
0
Partial oscillator power down for faster startup (100 nA nominal).
1 Full oscillator power down for lower power (0 nA nominal).
5 ILOFREQ Selects oscillator nominal frequency.
0
32 kHz
1 1 kHz
3:0 Freq Trim[3:0] These bits trim the oscillator frequency.
Individual Register Names and Addresses:
1,E9h
ILO_TR : 1,E9h
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RW : 08
Bit Name PD_MODE ILOFREQ Freq Trim[3:0]
Bit Name Description
[+] Feedback