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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Interrupt Controller
5.3.6
INT_MSK2 Register
This register is used to enable the individual sources' ability
to create pending interrupts.
When an interrupt is masked off, the mask bit is '0'. The
interrupt still posts in the interrupt controller. Therefore,
clearing the mask bit only prevents a posted interrupt from
becoming a pending interrupt.
Bit 5: USB Wakeup.
’0’ is mask USB Wakeup interrupt. ‘1’
is unmask USB Wakeup interrupt.
Bit 4: Endpoint8.
’0’ is mask USB Endpoint8 interrupt. ‘1’ is
unmask USB Endpoint8 interrupt.
Bit 3: Endpoint7.
’0’ is mask USB Endpoint7 interrupt. ‘1’ is
unmask USB Endpoint7 interrupt.
Bit 2: Endpoint6.
’0’ is mask USB Endpoint6 interrupt. ‘1’ is
unmask USB Endpoint6 interrupt.
Bit 1: Endpoint5.
’0’ is mask USB Endpoint5 interrupt. ‘1’ is
unmask USB Endpoint5 interrupt.
Bit 0: Endpoint4.
’0’ is mask USB Endpoint4 interrupt. ‘1’ is
unmask USB Endpoint4 interrupt.
For additional information, refer to the
5.3.7
INT_SW_EN Register
The Interrupt Software Enable Register (INT_SW_EN) is
used to enable software interrupts.
Bit 0: ENSWINT.
This bit is a special non-mask bit that
controls the behavior of the INT_CLR0 register. See the
INT_CLR0 register in this section for more information.
For additional information, refer to the
5.3.8
INT_VC Register
The Interrupt Vector Clear Register (INT_VC) returns the
next pending interrupt and clears all pending interrupts when
written.
Bits 7 to 0: Pending Interrupt[7:0].
When the register is
read, the
of the highest priority
pending interrupt is returned. For example, if the GPIO and
I2C interrupts were pending and the INT_VC register was
read, the value 14h is read. However, if no interrupts were
pending, the value 00h is returned. This is the reset vector in
the interrupt table; however, reading 00h from the INT_VC
register is not considered an indication that a system reset is
pending. Rather, reading 00h from the INT_VC register sim-
ply indicates that there are no pending interrupts. The high-
est priority interrupt, indicated by the value returned by a
read of the INT_VC register, is removed from the list of
pending interrupts when the M8C services an interrupt.
Reading the INT_VC register has limited usefulness. If inter-
rupts are enabled, a read to the INT_VC register is not able
to determine that an interrupt was pending before the inter-
rupt was actually taken. However, while in an interrupt ser-
vice routine, a user may wish to read the INT_VC register to
see the next interrupt. When the INT_VC register is written
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,DEh
USB Wakeup
Endpoint8
Endpoint7
Endpoint6
Endpoint5
Endpoint4
RW : 00
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,E1h
ENSWINT
RW : 0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,E2h
Pending Interrupt[7:0]
RC : 00
LEGEND
Clearable register or bits.
Summary of Contents for PSoC CY8CTMG20 Series
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Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
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