Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 95 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 95
TrueTouch Module
11.2.7 CS_STAT Register
The TrueTouch Status Register (CS_STAT) controls True-
Touch counter options.
Status Bits 7 to 4.
The posted TrueTouch interrupts are the
corresponding status bits in this register. Interrupt clearing is
performed by clearing the associated status bit. Status can
only be updated while the block is enabled and running. All
status bits are cleared when the block is disabled.
Bit 7: INS.
Input Status. Reading a ‘1’ indicates a rising
edge on the selected input was detected. Reading a ‘0’ indi-
cates that this event did not occur. This bit is cleared by writ-
ing a ‘0’ to this bit position. Writing a ‘1’ has no effect.
Bit 6: COLS. Counter Carry Out Low Status. Reading a ‘1’
indicates an overflow occurred in the Counter Low block.
Reading a ‘0’ indicates that this event did not occur. This bit
is cleared by writing a ‘0’ to this bit position. Writing a ‘1’ has
no effect.
Bit 5: COHS. Counter Carry Out High Status. Reading a ‘1’
indicates an overflow occurred in the Counter High block.
Reading a ‘0’ indicates that this event did not occur. This bit
is cleared by writing a ‘0’ to this bit position. Writing a ‘1’ has
no effect.
Bit 4: PPS. Pulse Width/Period Status. Reading a ‘1’ indi-
cates the completion of a pulse width or period measure-
ment (as defined by the MODE[1:0] bits in CS_CR0). This
bit is cleared by writing a ‘0’ to this bit position. Writing a ‘1’
has no effect.
Mask Bits 3 to 0. Never modify the interrupt mask bits
while the block is enabled. If modification to bits 3 to 0 is
necessary while the block is enabled, make certain that the
status bits, bits 7 to 4, are not accidentally cleared. Do this
by writing a ‘1’ to all of the status bits when writing to the
mask bits.
Bit 3: INM. Input Interrupt Mask. When this bit is a ‘1’, a ris-
ing edge event on the input asserts the block interrupt.
When this bit is a ‘0’, this event is masked.
Bit 2: COLM. Counter Carry Out Low Mask. When this bit
is a ‘1’, a carry out from the counter low block asserts the
block interrupt. When this bit is a ‘0’, this event is masked.
Bit 1: COHM.
Counter Carry Out High Mask. When this bit
is a ‘1’, a carry out from the counter high block asserts the
block interrupt. When this bit is a ‘0’, this event is masked.
Bit 0: PPM. Pulse Width/Period Mask. When this bit is a ‘1’,
the completion of a pulse width or period measurement
asserts the block interrupt. When this bit is a ‘0’, this event is
masked.
For additional information, refer to the CS_STAT register on
page 217 .
11.2.8 CS_TIMER Register
The TrueTouch Timer Register (CS_TIMER) sets the timer
count value.
Bits 6 to 0: Timer Count Value[6:0].
The 6-bit value in this
register sets the initial count value for the timer.
For additional information, refer to the CS_TIMER register
on page 218 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,A6h CS_STAT INS COLS COHS PPS INM COLM COHM PPM # : 00
LEGEND
# Access is bit specific.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,A7h CS_TIMER Timer Count Value[6:0] RW : 00
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