PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
123
I2C Slave
15.3.2
I2C_XSTAT Register
The I
2
C Extended Status Register (I2C_XSTAT) reads
enhanced feature status. All bits are read only. When the
bits of I2C_XCFG are left in their reset state, the block is in
compatibility mode, and this register is not in use.
Bit 1: Dir.
This bit indicates the direction of the current
transfer. A ‘1’ indicates a master read, and a ‘0’ indicates a
master write. It is only valid when the Slave Busy bit (bit 0) is
set to ‘1’.
Bits 0: Slave Busy.
This bit is set upon a hardware
address compare and is reset upon the following stop sig-
nal. Poll this bit to determine when the slave is busy and the
buffer module is being accessed.
For additional information, refer to the
15.3.3
I2C_ADDR Register
The I
2
C Slave Address Register (I2C_ADDR) holds the
slave’s 7-bit address. All bits are RW.
Note
When hardware address compare mode is not
enabled in the I2C_XCFG register, this register is not in use.
Bits 6 to 0: Slave Address[6:0]
. These 7 bits hold the
slave’s own device address.
For additional information, refer to the
15.3.4
I2C_BP Register
The I
2
C Base Address Pointer Register (I2C_BP) contains
the base address value of the RAM data buffer.
Note
When in compatibility mode, this register is not in use.
Bits 4 to 0: I2C Base Pointer[4:0].
In the EZI2C protocol,
the first data byte after the slave address transaction in write
mode is the base address for subsequent reads and writes
and it is transferred directly into this register. If the desired
transaction is a master write to the slave, subsequent bytes
are written to the RAM buffer starting with this address and
auto incremented (see
).
In case of a read, a Start or Restart must be issued and the
read location starts with this address and again subsequent
read addresses are auto incremented as pointed to by the
I2C_CP register value. The value of this register is modified
only at the beginning of every I
2
C write transaction. The I
2
C
master must always supply a value for this register in the
first byte of data after the slave’s address in a given write
transaction. If performing reads, the master need not set the
value of this register. The current value of this register is
also used directly for reads.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,C9h
Dir
Slave Busy
R : 0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,CAh
Slave Address[6:0]
RW : 00
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,CBh
I2C Base Pointer[4:0]
R : 00
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
