Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 229 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 229
I2C_BP
0,CBh
21.3.41 I2C_BP
I
2
C Base Address Pointer Register
This register contains the base address value of the RAM data buffer and is read only.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the
Register Definitions on page 122 in the
I2C Slave chapter.
4:0 I2C Base Pointer[4:0] In the EZI2C protocol, the first data byte after the slave address transaction in write mode is the base
address for subsequent reads and writes and it is transferred directly into this register. If the desired
transaction is a master write to the slave, subsequent bytes are written to the RAM buffer starting with
this address and auto incremented (see I2C_CP register). In case of a read, a Start or Restart must
be issued and the read location starts with this address and again subsequent read addresses are
auto incremented as pointed to by the I2C_CP register value.
The value of this register is modified only at the beginning of every I2C write transaction. The I2C
master must always supply a value for this register in the first byte of data after the slave’s address in
a given write transaction. If performing reads, the master need not set the value of this register. The
current value of this register is also used directly for reads.
Individual Register Names and Addresses: 0,CBh 0,D0h
I2C_BP : 0,CBh
7 6 5 4 3 2 1 0
Access : POR R : 00
Bit Name I2C Base Pointer[4:0]
Bit Name Description
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