122
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
I2C Slave
15.3
Register Definitions
The registers shown here are associated with I
2
C Slave and are listed in address order. Each register description has an
associated register table showing the bit structure for that register. The grayed out bits in the tables are reserved bits and are
not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0’. For a complete table of I
2
C
registers, refer to the
“Summary Table of the System Resource Registers” on page 106
.
15.3.1
I2C_XCFG Register
The I
2
C Extended Control Register (I2C_XCFG) configures
enhanced features. When all bits are left in the default reset
state of ‘0’, the block operates in compatibility mode. Bits 0
through 3 (except bit 2) are RW.
The Enable bit (bit 0) of the I2C_CFG (0,D6h) register
should be set to 1'b1 for the I
2
C enhanced features to work.
Bit 3: No BC Int.
In compatibility mode, every received or
transmitted byte generates a byte complete interrupt. This is
also true in buffered mode regardless of whether the bus is
stalled or not.
Note
When this bit is set to a ‘1’, A BC interrupt is not
enabled for any data byte that is automatically ACK’ed (i.e.,
does not require the bus to stall). A BC interrupt is always
generated on any stall so the CPU takes the appropriate
action. When the bit is set, it is possible to implement packet
transfers without CPU intervention by enabling an interrupt
upon the Stop detect.
Bit 1: Buffer Mode.
This bit determines the operation
mode of the enhanced buffer module. The following table
describes the available modes.
Bit 0: HW Addr En.
When this bit is set to a ‘1’, hardware
address compare is enabled. Upon a compare, the address
is automatically ACK‘ed, and upon a mismatch, the address
is automatically NACK‘ed and the hardware reverts to an
idle state waiting for the next Start detection. You must con-
figure the compare address in the I2C_ADDR register.
When this bit is a ‘0’, bit 3 of the I2C_SCR register is set and
the bus stalls, and the received address is available in the
I2C_DR register to enable the CPU to do a firmware
address compare. The functionality of this bit is independent
of the data buffering mode.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,C8h
No BC Int
Buffer Mode HW Addr EN
RW : 0
HW Addr
EN
Buffer
Mode
No BC lnt
Byte Complete
Interrupt
Clock (SCL)
Stalling
On
On
On
No interrupt.
No stalling.
Off
Interrupt generated
upon every byte.
a
a. Non-address BC interrupts are only posted if the BC bit is cleared in
I2C_SCR. Putting the M8C to sleep without clearing the BC bit in
I2C_SCR will mask I
2
C interrupts. This will stall the I
2
C bus.
On
Off
On
Interrupt generated
upon every byte.
b
b. Enabling No BC Int has no affect when HW Addr En is enabled and buff-
er mode is disabled, even at address byte. The reason is that the receive/
transmit bit must be set by the CPU. In the case of transmit operation,
the byte to transmit must be loaded to the I2C_DATA register.
SCL stalls at
each byte.
Off
Interrupt generated
upon every byte.
Off
On
On
Generated only at
address byte.
c
c. Enabling No BC Int has no affect only at address byte in this configura-
tion. The reason is that the CPU must write to the ACK bit in the
I2C_SCR register to ACK/NACK the address byte.
SCL stalls only
at address byte.
Off
Interrupt generated
upon every byte.
a
Off
Off
On
Interrupt generated
upon every byte.
d
d. Enabling No BC Int has no affect in compatibility mode.
SCL stalls at
every byte.
Off
Interrupt generated
upon every byte.
Buffer
Mode
Name
Description
0
Compatible
There is no buffering in the default compatibility
mode. The
I
2
C
bus is stalled upon every received
or transmitted byte, including address bytes. The
CPU is required to process the interrupt and write
or read the data and status as required to continue
the operation.
1
EZI2C
The
I
2
C
slave appears as a 32-byte RAM inter-
face to an external master. A specific protocol must
be followed, in which the master controls the RAM
pointer for both read and write operations. The
I
2
C
bus is never stalled. Receive ACKs are auto-
matically generated. The CPU is responsible for
putting valid data into the RAM for external reads,
and for reading received data.
Summary of Contents for PSoC CY8CTMG20 Series
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