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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
I2C_XCFG
0,C8h
21.3.38 I2C_XCFG
I
2
C Extended Configuration Register
This register configures enhanced features. The Enable bit (bit 0) of the
(0,D6h) register should be set to 1'b1 for
the I2C enhanced features to work.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the
Register Definitions on page 122
in the
I2C Slave chapter
.
3
No BC Int
In compatibility mode, every received or transmitted byte generates a Byte Complete Interrupt. This is
also true in buffered mode regardless of whether the bus is stalled or not.
Note
When this bit is set to a ‘1’, A BC interrupt is not enabled for any data byte that is automatically
ACK’ed (i.e., does not require the bus to stall). A BC interrupt is always generated upon any stall so
the CPU takes the appropriate action. When the bit is set, it is possible to implement packet transfers
without CPU intervention by enabling an interrupt upon the Stop detect.
1
Buffer Mode
This bit determines the operation mode of the enhanced buffer module. The following table describes
the available modes.
0
HW Addr En
When this bit is set to a ‘1’, hardware address compare is enabled. When enabled, bit 3 in the
I2C_SCR register is not set. Upon a compare, the address is automatically ACK’ed, and upon a mis-
match, the address is automatically NACK’ed and the hardware reverts to an idle state waiting for the
next Start detection. You must configure the compare address in the I2C_ADDR register. When this
bit is a ‘0’, bit 3 of the I2C_SCR register is set and the bus stalls, and the received address is avail-
able in the I2C_DR register to enable the CPU to do a firmware address compare. The functionality of
this bit is independent of the data buffering mode.
Individual Register Names and Addresses:
0,C8h
I2C_XCFG: 0,C8h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
Bit Name
No BC Int
Buffer Mode
HW Addr En
Bit
Name
Description
Buffer
Mode
Name
Description
0
Compatible
There is no buffering in the default compatibility
mode. The I2C bus is stalled upon every received
or transmitted byte, including address bytes. The
CPU is required to process the interrupt and write or
read the data and status as required to continue the
operation.
1
EZI2C
The I2C slave appears as a 32-byte RAM interface
to an external master. A specific protocol must be
followed, in which the master controls the RAM
pointer for both read and write operations. The I2C
bus is never stalled. Receive ACKs are automati-
cally generated. The CPU is responsible for putting
valid data into the RAM for external reads, and for
reading received data.
Summary of Contents for PSoC CY8CTMG20 Series
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Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
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Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
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