PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
173
Full-Speed USB
20.3.5
EP0_CR Register
The Endpoint Control Register (EP0_CR) is used to config-
ure endpoint 0.
Because both firmware and the SIE are allowed to write to
the Endpoint 0 Control and Count registers, the SIE pro-
vides an interlocking mechanism to prevent accidental over-
writing of data. When the SIE writes to these registers they
are locked and the processor cannot write to them until after
reading the EP0_CR register. Writing to this register clears
the upper four bits regardless of the value written.
Note
The register lock is removed when the following M8C
instructions are used to write the EP0_CR register as these
instructions generate a read (IOR_) signal, which causes
the lock to be removed even without the firmware actually
reading the EP0_CR register.
mov reg[expr], expr
mov reg[X+expr], expr
Bit 7: Setup Received.
When set, this bit indicates a valid
setup packet was received and ACK’ed. This bit is forced
high from the start of the data packet phase of the setup
transaction, until the start of the ACK packet returned by the
SIE. The CPU is prevented from clearing this bit during this
interval. After this interval, the bit remains set until cleared
by firmware. While this bit is set to '1', the CPU cannot write
to the EP0_DRx registers. This prevents firmware from
overwriting an incoming setup transaction before firmware
has a chance to read the setup data. This bit is cleared by
any non-locked writes to the register.
Bit 6: IN Received.
When set, this bit indicates a valid IN
packet has been received. This bit is updated to '1' after the
host acknowledges an IN data packet. When clear, this bit
indicates either no IN has been received or that the host did
not acknowledge the IN data by sending an ACK hand-
shake. It is cleared by any non-locked writes to the register.
Bit 5: OUT Received.
When set, this bit indicates a valid
OUT packet has been received and ACK’ed. This bit is
updated to '1' after the last received packet in an OUT trans-
action. When clear, this bit indicates no OUT has been
received. It is cleared by any non-locked writes to the regis-
ter.
Bit 4: ACK’ed Transaction.
This bit is set whenever the
SIE engages in a transaction to the register's endpoint that
completes with an ACK packet. This bit is cleared by any
non-locked writes to the register.
Bits 3 to 0: Mode[3:0].
The mode bits control how the USB
SIE responds to traffic and how the USB SIE changes the
mode of that endpoint as a result of host packets to the end-
point.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,36h
Setup
Received
IN Received
OUT
Received
ACK’ed
Transaction
Mode[3:0]
# : 00
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
