286
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
IMO_TR1
1,FAh
21.4.27 IMO_TR1
Internal Main Oscillator Trim Register 1
This register is used to fine tune the IMO frequency.
It is strongly recommended that the user not alter this register’s values
.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved
bits should always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on page 64
in the
Internal Main Oscillator chapter.
7:0
FineTrim[2:0]
These bits provide ability to fine tune the IMO frequency.
These values are normally only changed by the oscillator-locking function. These are the lower
3 bits of the 11-bit oscillator trim. IMO_TR holds the MSb.
Individual Register Names and Addresses:
1,FAh
IMO_TR1 : 1,FAh
7
6
5
4
3
2
1
0
Access : POR
W : 0
Bit Name
FineTrim[2:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
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Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
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Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
