Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 78 / 308

78 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Sleep and Watchdog
10.3.3 SLP_CFG2 Register
The Sleep Configuration Register (SLP_CFG2) holds the
configuration for I2C sleep, deep sleep, and buzz.
Bits 3 and 2: ALT_Buzz[1:0]. These bits control additional
selections for POR/LVD buzz rates. These are lower rates
than the compatibility mode to provide for lower average
power.
‘00’ - Compatibility mode, buzz rate determined by PSSDC
bits.
‘01’ - Duty cycle is 1/32768.
‘10’ - Duty cycle is 1/8192.
‘11’ - Reserved.
Bit 1: I2C_ON. This bit enables the standby regulator in
sleep at a level sufficient to supply the I2C circuitry. It is
independent of the LSO_OFF bit.
Bit 0: LSO_OFF: This bit disables the LSO oscillator when
in sleep state. By default, the LSO oscillator runs in sleep.
When this bit is ‘0’, the standby regulator is active at a power
level to supply the LSO and Sleep timer circuitry and the
LSO is enabled. When this bit is ‘1’, the LSO is disabled in
sleep, which in turn, disables the Sleep Timer, Watchdog
Timer, and POR/LVD buzzing activity in sleep. If I2C_ON is
not enabled and this bit is set, the device is in the lowest
power deep sleep mode. Only a GPIO interrupt awakens the
device from deep sleep mode.
For additional information, refer to the SLP_CFG2 register
on page 284 .
10.3.4 SLP_CFG3 Register
The Sleep Configuration Register (SLP_CFG3) holds the
configuration of the wakeup sequence taps.
It is strongly recommended to not alter this register set-
ting
.
Bit 6: DBL_TAPS. When this bit is set, all the tap values
(T0, T1, and T2) are doubled for the wakeup sequence.
Bits 5 and 4: T2TAP[1:0]. These bits control the duration
of the T2-T4 sequence (see Figure 10-2 on page 75 ) by
selecting a tap from the WakeupTimer. Note The T2 delay is
only valid for the wakeup sequence. It is not used for the
buzz sequence.
‘00’ - 1 µs
‘01’ - 2 µs
‘10’ - 5 µs
‘11’ - 10 µs
Bits 3 and 2: T1TAP[1:0]. These bits control the duration of
the T1-T2 sequence (see Figure 10-2 on page 75 ) by select-
ing a tap from the Wakeup Timer.
‘00’ - 3 µs
01’ - 4 µs
‘10’ - 5 µs
‘11’ - 10 µs
Bits 1 and 0: T0TAP[1:0]. These bits control the duration
of the T0-T1 sequence (see Figure 10-2 on page 75 ) by
selecting a tap from the Wakeup Timer.
‘00’ - 10 µs
‘01’ - 14 µs
‘10’ - 20 µs
‘11’ - 30 µs
For additional information, refer to the SLP_CFG3 register
on page 285 .
10.3.5 Related Registers
■
INT_MSK0 Register on page 51 .
■
OSC_CR0 Register on page 113 .
■
ILO_TR Register on page 68 .
■
CPU_SCR0 Register on page 138 .
■
CPU_SCR1 Register on page 137 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,ECh SLP_CFG2 ALT_Buzz [1:0] I2C_ON LSO_OFF RW : 00
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,EDh SLP_CFG3 DBL_TAPS T2TAP [1:0] T1TAP [1:0] T0TAP [1:0] RW : 0x7F
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